From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1133.google.com (mail-yw1-x1133.google.com [IPv6:2607:f8b0:4864:20::1133]) by sourceware.org (Postfix) with ESMTPS id 3F4B63858CD1 for ; Mon, 13 Nov 2023 06:58:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3F4B63858CD1 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3F4B63858CD1 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::1133 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699858737; cv=none; b=qNkG4XIJPWK/mK8KZJjqIsyr0vFW0qt9a7HKoqPaM/9Cn8+JCYUanAFiwYDwUTMT4Byt+9l3lV/vSregDkabjDGgNGinfP1DyhSswhp+bgc4oYiz6h28gNuHZiKn39fMdxf2zGcWVivgi36PsFMj9eeQl5sTaOnJ3FSLiJbGSr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699858737; c=relaxed/simple; bh=ht3UX7vBmgpCDqi+z8K7HgUkPH3K7ndr5zrl8WNX9a4=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=Gek8KLiSOtQgn1HVNaNRyIVhAJP8ODV29ltF+F9aoXeVbZDXq2VXVHbs0tqZoUPVp3xt3IJJzwFR85y6NXBK+dBnFfI/Zj+iirfvI8GN3i3IqXSTj7nmgWX+U7ZoqnrPzEZoN451diPla1p1UJZcWVVHQpci0nf1Y/GNQ8aiSgc= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-yw1-x1133.google.com with SMTP id 00721157ae682-5a86b6391e9so49120677b3.0 for ; Sun, 12 Nov 2023 22:58:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699858735; x=1700463535; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=a86FggDeXk9ZDMtiiVF0EOsNAlxUcqWRkUJ077Cizdw=; b=URDRl+eN7jF9aqqTiQeoLOQIZsuZ4BWjScezJBbTkjzcj9ptFKEaw1LMk0s0ckMkEs F4MMHmfDGxWu3mRp0/IILI90p/8sT60CC0ZDOHxv8aRt5rmT6tYA+O6MsFiqHyaskhHS 8mJ0xNQeS4FCZCVtasFTmcBjvkO5pXEbphHYINmGc/sO40Eiqwv52U6CuyI1kOVDEId6 kkFa3SVPjSMOjgTao4WKE8SWWzMkC2IucLyNHtThKiWGkp8WFetKmMVEx8bRomc19rYB ZqoGh4PL2HHPa1WmNBY958KhXw1kd+Cw3QKcqy1sc1k4wTooIhgw3GIzzfumW3LT/a3B TbhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699858735; x=1700463535; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a86FggDeXk9ZDMtiiVF0EOsNAlxUcqWRkUJ077Cizdw=; b=pd9K0aDQNffGad5awVyRuyjm9usxcV1yTlxwVvm2KMzzTVT/49O2nh8bcVRva1Pin2 8ARsAL20E/DTCHj3vB0nIEjA1w4jJG7pq5zP8jPyDSBfmeKEBAirkKZuXnPI9Mv9cLtH hWwLUSRIzVSAfufrUn+9RvDa17rRcrn4YHH9C+kidJR7UdrTUxNS7dtpsGLMY1Wdbh/O bv9CedZzzXoKcCmfdDSaeQOJaGfTPgzKMXVrINeTh3bWfWzNM6camWAnnxffl0P/rkWf H8A8pRf0v3zTyVOYHXzInM8KYGXbrnoZEdp0WAPbUZwWrZDMgqW279u7O4mAiIFihsRk i6EQ== X-Gm-Message-State: AOJu0Yz8AYa2xvK807A19I6x2Y6QZKwpAkavENomom5Z68Oiv0Q49K2S GIB33aie4dWrkEkp/x4Cj9PjntNLd+mNnqy76fE= X-Google-Smtp-Source: AGHT+IHSh9iLxIPMRnDFe5so7Q4WaFn0dL/nKJbEaxwl/sIdyTr7hAdjJBWYoSc5gMomLX1S/ZUiSr2W0YtM/mwnFPc= X-Received: by 2002:a81:4746:0:b0:5ae:c0f2:cd42 with SMTP id u67-20020a814746000000b005aec0f2cd42mr6548052ywa.43.1699858735549; Sun, 12 Nov 2023 22:58:55 -0800 (PST) MIME-Version: 1.0 References: <20231110014158.371690-1-haochen.jiang@intel.com> In-Reply-To: From: Hongtao Liu Date: Mon, 13 Nov 2023 15:07:12 +0800 Message-ID: Subject: Re: [RFC] Intel AVX10.1 Compiler Design and Support To: Richard Biener Cc: Haochen Jiang , gcc-patches@gcc.gnu.org, hongtao.liu@intel.com, ubizjak@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Nov 10, 2023 at 6:15=E2=80=AFPM Richard Biener wrote: > > On Fri, Nov 10, 2023 at 2:42=E2=80=AFAM Haochen Jiang wrote: > > > > Hi all, > > > > This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex5= 12 > > support, it makes a lot easier to add them comparing to the August vers= ion. > > Detail for AVX10 is shown below: > > > > Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specific= ation > > It describes the Intel Advanced Vector Extensions 10 Instruction Set > > Architecture. > > https://cdrdv2.intel.com/v1/dl/getContent/784267 > > > > The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical= Paper > > It provides introductory information regarding the converged vector ISA= : Intel > > Advanced Vector Extensions 10. > > https://cdrdv2.intel.com/v1/dl/getContent/784343 > > > > Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" IS= As in > > the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enable > > anything at first. At the end of the option handling, we will check whe= ther > > the two bits are set. If AVX10.1-256 is set, we will set the AVX512 rel= ated > > ISA bits. AVX10.1-512 will further set EVEX512 ISA bit. > > > > It means that AVX10 options will be separated from the existing AVX512 = and the > > newly added -m[no-]evex512 options. AVX10 and AVX512 options will contr= ol > > (enable/disable/set vector size) the AVX512 features underneath indepen= dently. > > If there=E2=80=99s potential overlap or conflict between AVX10 and AVX5= 12 options, > > some rules are provided to define the behavior, which will be described= below. > > > > avx10.1 option will be provided as an alias of avx10.1-256. > > > > In the future, the AVX10 options will imply like this: > > > > AVX10.1-256 <---- AVX10.1-512 > > ^ ^ > > | | > > > > AVX10.2-256 <---- AVX10.2-512 > > ^ ^ > > | | > > > > AVX10.3-256 <---- AVX10.3-512 > > ^ ^ > > | | > > > > Each of them will have its own option to enable/disabled corresponding > > features. The alias avx10.x will also be provided. > > > > As mentioned in August version RFC, since we lean towards the adoption = of > > AVX10 instead of AVX512 from now on, we don=E2=80=99t recommend users t= o combine the > > AVX10 and legacy AVX512 options. > > I wonder whether adoption could be made easier by also providing a > -mavx10[.0] level that removes some of the more obscure sub-ISA requireme= nts > to cover more existing implementations (I'd not add -mavx10.0-512 here). > I'd require only skylake-AVX512 features here, basically all non-KNL AVX5= 12 > CPUs should have a "virtual" AVX10 level that allows to use that feature = set, We have -mno-evex512 can cover those cases, so what you want is like a simple alias of "-march=3Dskylake-avx512 -mno-evex512"? > restricted to 256bits so future AVX10-256 implementations can handle it > as well as all existing (and relevant, which excludes KNL) AVX512 > implementations. > > Otherwise AVX10 is really a hard sell (as AVX512 was originally). It's a rebranding of the existing AVX512 to AVX10, AVX10.0 just complicated things further(considering we already have x86-64-v4 which is different from skylake-avx512). > > > However, we would like to introduce some > > simple rules for user when it comes to combination. > > > > 1. Enabling AVX10 and AVX512 at the same command line with different ve= ctor > > size will lead to a warning message. The behavior of the compiler will = be > > enabling AVX10 with longer, i.e., 512 bit vector size. > > > > If the vector sizes are the same (e.g. -mavx10.1-256 -mavx512f -mno-eve= x512, > > -mavx10.1-512 -mavx512f), it will be valid with the corresponding vecto= r size. > > > > 2. -mno-avx10.1 option can=E2=80=99t disable any features enabled by AV= X512 options or > > impact the vector size, and vice versa. The compiler will emit warnings= if > > necessary. > > > > For the auto dispatch support including function multi versioning, func= tion > > attribute usage, the behavior will be identical to compiler options. > > > > If you have any questions, feel free to ask in this thread. > > > > Thx, > > Haochen > > > > --=20 BR, Hongtao