From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1131.google.com (mail-yw1-x1131.google.com [IPv6:2607:f8b0:4864:20::1131]) by sourceware.org (Postfix) with ESMTPS id D649D3858D20 for ; Wed, 9 Aug 2023 02:07:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D649D3858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x1131.google.com with SMTP id 00721157ae682-58688a0adbbso68297117b3.0 for ; Tue, 08 Aug 2023 19:07:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1691546827; x=1692151627; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=fdjQWnVAONpPw+9w1JZgnUIamWtklJDuIztX1sgpRMA=; b=nZbNJezk7jh24AxevG3QH3ZgQ9FYSeVEsdCXfDBSOmk8JqJDyOmdVDufXpTU74ImB4 mpln6QGal/n1RWRt+YmM6OiKpJROduymynrsUOBVCiu9dvOZxQQQCUU/9MIzrpdxFSK0 nzyevop6bVfUit6ml48BqGOvoVNNLOFetvAAJUOAMZzHB4DXaM2aIXdkVwaAzbwRaYND 0SDO74KU9o0uwv8H0GDqibVbLi9XAitv9RwF5S7bCZdmICrVWnrP5BmCVBtfbZ1atO1e 27H+VBrZX6aughih0TdOMJ7mOOUSnt8k1cQt3xMuJGi/piEntQjz/1MZ/YJS7O703bsH yhFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691546827; x=1692151627; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fdjQWnVAONpPw+9w1JZgnUIamWtklJDuIztX1sgpRMA=; b=IB4R/KMsUerNhlmeqVJXUwHxiE9ACurNmUKBze4XLQ7b63rYFzevGIcmhBgYovReYq bklsC6rEJcGaNnzGOc8O3YGYuBE9CKUl9tEBrPhPurYe3+DOgOokCGeM3oJZtRi3iFe9 g8Y6TOavIBFxcrU0PJfsayRPwnoXb1gebPZq2vD6Q5H+SATHBO1b7c/Eq6EX3wzExCs4 SXMOC1LrxAOvih5iQwAtRa9MRenRRRENsgZR3u9+4me5vCzxnh08F1BwXdfQYtHmMNiy W70424rGFTB7kVAzfzB6gw9+imAHemPbNn/iuWjD/w/m36/XjN5k69+2YTOM/ru+qLys 0buA== X-Gm-Message-State: AOJu0Yytd1IlYgK9pqE+8qcRusPcR1b0OtxSwFNBZW6TBt5wzBgzWmp2 EdmqYIAy3zghv/GQOGbm3v4r24BhIztf0nyXKPY= X-Google-Smtp-Source: AGHT+IHiQ+a0N4RxZeLniCpUNc/Ttd4k/HHmHBkLGdLNrMvQl/xik7W91iFKvQBljnEhuMHLftyGtAtSTRIp2zAjKR0= X-Received: by 2002:a25:6d04:0:b0:d0f:b553:8284 with SMTP id i4-20020a256d04000000b00d0fb5538284mr1174438ybc.20.1691546827023; Tue, 08 Aug 2023 19:07:07 -0700 (PDT) MIME-Version: 1.0 References: <20230808071312.1569559-1-haochen.jiang@intel.com> In-Reply-To: From: Hongtao Liu Date: Wed, 9 Aug 2023 10:06:55 +0800 Message-ID: Subject: Re: Intel AVX10.1 Compiler Design and Support To: Richard Biener Cc: "Jiang, Haochen" , Jakub Jelinek , "gcc-patches@gcc.gnu.org" , "ubizjak@gmail.com" , "Liu, Hongtao" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Aug 8, 2023 at 8:45=E2=80=AFPM Richard Biener via Gcc-patches wrote: > > On Tue, Aug 8, 2023 at 10:15=E2=80=AFAM Jiang, Haochen via Gcc-patches > wrote: > > > > Hi Jakub, > > > > > So, what does this imply for the current ISAs? > > > > AVX10 will imply AVX2 on the ISA level. And we suppose AVX10 is an > > independent ISA feature set. Although sharing the same instructions and > > encodings, AVX10 and AVX512 are conceptual independent features, which > > means they are orthogonal. > > > > > The expectations in lots of config/i386/* is that -mavx512f / TARGET_= AVX512F > > > means 512 bit vector support is available and most of the various -ma= vx512XXX > > > options imply -mavx512f (and -mno-avx512f turns those off). And if > > > -mavx512vl / TARGET_AVX512VL isn't available, tons of places just use > > > 512-bit EVEX instructions for 256-bit or 128-bit stuff (mostly to be = able to > > > access [xy]mm16+). > > > > For AVX10, the 128/256/scalar version of the instructions are always th= ere, and > > also for [xy]mm16+. 512 version is "optional", which needs user to indi= cate them > > in options. When 512 version is enabled, 128/256/scalar version is also= enabled, > > which is kind of reverse relation between the current AVX512F/AVX512VL. > > > > Since we take AVX10 and AVX512 are orthogonal, we will add OR logic for= the current > > pattern, which is shown in our AVX512DQ+VL sample patches. > > Hmm, so it sounds like AVX10 is currently, at the 10.1 level, a way to sp= ecify > AVX512F and AVX512VL "differently", so wouldn't it make sense to make it In the future there're plantfomrs only support AVX10.x-256, but not AVX512 stuffs, it doesn't make much sense on that platfrom to disable part of AVX512. We really want to make AVX10.x a indivisible features, just like other individual CPUID. > complement those only so one can use, say, -mavx10 -mno-avx512bf16 to dis= able > parts of the former AVX512 ISA one doesn't like to get code generated for= ? > -mavx10 would then enable all the existing sub-AVX512 ISAs? Another alternative solution is > > > > Sure, I expect all AVX10.N CPUs will have AVX512VL CPUID, will they h= ave > > > AVX512F CPUID even when the 512-bit vectors aren't present? What happ= ens if > > > one mixes the -mavx10* options together with -mno-avx512vl or similar > > > options? Will -mno-avx512f still imply -mno-avx512vl etc.? > > > > For the CPUID part, AVX10 and AVX512 have different emulation. Only Xeo= n Server > > will have AVX512 related CPUIDs for backward compatibility. For GNR, it= will be > > AVX512F, AVX512VL, AVX512CD, AVX512BW, AVX512DQ, AVX512_IFMA, AVX512_VB= MI, > > AVX512_VNNI, AVX512_BF16, AVX512_BITALG, AVX512_VPOPCNTDQ, AV512_VBMI2, > > AVX512_FP16. Also, it will have AVX10 CPUIDs with 512 bit support set. = Atom Server and > > client will only have AVX10 CPUIDs with 256 bit support set. > > > > -mno-avx512f will still imply -mno-avx512vl. > > > > As we mentioned below, we don't recommend users to combine the AVX10 an= d legacy > > AVX512 options. We understand that there will be different opinions on = what should > > compiler behave on some controversial option combinations. > > > > If there is someone mixes the options, the golden rule is that we are u= sing OR logic. > > Therefore, enabling either feature will turn on the shared instructions= , no matter the other > > feature is not mentioned or closed. That is why we are emitting warning= for some scenarios, > > which is also mentioned in the letter. > > I'm refraining from commenting on the senslesness of AVX10 as you're > likely on the same > receiving side as us. > > Thanks, > Richard. > > > Thx, > > Haochen > > > > > > > > Jakub > > --=20 BR, Hongtao