From: "H.J. Lu" <hjl.tools@gmail.com>
To: Uros Bizjak <ubizjak@gmail.com>
Cc: Kirill Yukhin <kirill.yukhin@gmail.com>,
gcc-patches List <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
Date: Wed, 19 Oct 2011 16:34:00 -0000 [thread overview]
Message-ID: <CAMe9rOo+gf6UbzDnV7vJ4Fin8cNasCUu6i9NfZ+mejH9a0Dy7A@mail.gmail.com> (raw)
In-Reply-To: <CAFULd4Yf478LBLh+NgyVqvHsPVAFM=uaQ1e2jbZ0PLgT2Ny4-Q@mail.gmail.com>
On Wed, Oct 19, 2011 at 6:21 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Wed, Oct 19, 2011 at 3:07 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
>
>> Here is (almost obvous) patch, which fixes PR50766.
>>
>> ChangeLog entry:
>> 2011-10-19 Kirill Yukhin <kirill.yukhin@intel.com>
>>
>> * config/i386/i386.md (bmi_bextr_<mode>): Update register/
>> memory operand order.
>> (bmi2_bzhi_<mode>3): Ditto.
>> (bmi2_pdep_<mode>3): Ditto.
>> (bmi2_pext_<mode>3): Ditto.
Please mention PR #.
>> Bootstrapped, test (from bug) passing.
>>
>> Could you please have a look?
>
> Please also add the testcase from the PR. You can use { dg-do
> assemble }, but you have to check for BMI2 effective target support.
>
> BTW: I can't find BMI2 instruction reference documentation, so I'm
It is in Intel AVX spec:
http://software.intel.com/en-us/avx/
> just rubberstamping the patch as obvious.
>
--
H.J.
next prev parent reply other threads:[~2011-10-19 15:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-19 13:50 Kirill Yukhin
2011-10-19 14:38 ` Uros Bizjak
2011-10-19 16:34 ` H.J. Lu [this message]
2011-10-20 7:36 ` Kirill Yukhin
2011-10-20 7:43 ` Uros Bizjak
2011-10-20 8:36 ` Kirill Yukhin
2011-10-20 21:04 ` H.J. Lu
2011-10-21 5:53 ` Kirill Yukhin
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