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Date: Wed, 19 Oct 2011 16:34:00 -0000
Message-ID: <CAMe9rOo+gf6UbzDnV7vJ4Fin8cNasCUu6i9NfZ+mejH9a0Dy7A@mail.gmail.com>
Subject: Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
From: "H.J. Lu" <hjl.tools@gmail.com>
To: Uros Bizjak <ubizjak@gmail.com>
Cc: Kirill Yukhin <kirill.yukhin@gmail.com>, gcc-patches List <gcc-patches@gcc.gnu.org>
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On Wed, Oct 19, 2011 at 6:21 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Wed, Oct 19, 2011 at 3:07 PM, Kirill Yukhin <kirill.yukhin@gmail.com> =
wrote:
>
>> Here is (almost obvous) patch, which fixes PR50766.
>>
>> ChangeLog =A0entry:
>> 2011-10-19 =A0Kirill Yukhin =A0<kirill.yukhin@intel.com>
>>
>> =A0 =A0 =A0 =A0* config/i386/i386.md (bmi_bextr_<mode>): Update register/
>> =A0 =A0 =A0 =A0memory operand order.
>> =A0 =A0 =A0 =A0(bmi2_bzhi_<mode>3): Ditto.
>> =A0 =A0 =A0 =A0(bmi2_pdep_<mode>3): Ditto.
>> =A0 =A0 =A0 =A0(bmi2_pext_<mode>3): Ditto.

Please mention PR #.

>> Bootstrapped, test (from bug) passing.
>>
>> Could you please have a look?
>
> Please also add the testcase from the PR. You can use =A0{ dg-do
> assemble }, but you have to check for BMI2 effective target support.
>
> BTW: I can't find BMI2 instruction reference documentation, so I'm

It is in Intel AVX spec:

http://software.intel.com/en-us/avx/

> just rubberstamping the patch as obvious.
>

--=20
H.J.