From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3466 invoked by alias); 20 Mar 2012 19:26:22 -0000 Received: (qmail 3354 invoked by uid 22791); 20 Mar 2012 19:26:20 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-qc0-f175.google.com (HELO mail-qc0-f175.google.com) (209.85.216.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 20 Mar 2012 19:26:00 +0000 Received: by qcso7 with SMTP id o7so193256qcs.20 for ; Tue, 20 Mar 2012 12:25:59 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.106.83 with SMTP id w19mr461038qco.97.1332271557194; Tue, 20 Mar 2012 12:25:57 -0700 (PDT) Received: by 10.229.89.137 with HTTP; Tue, 20 Mar 2012 12:25:57 -0700 (PDT) In-Reply-To: References: <201203200951.07678.ebotcazou@adacore.com> <20120320085828.GP16117@tyan-ft48-01.lab.bos.redhat.com> <20120320111948.GQ16117@tyan-ft48-01.lab.bos.redhat.com> Date: Tue, 20 Mar 2012 19:26:00 -0000 Message-ID: Subject: Re: PATCH: Properly generate X32 IE sequence From: "H.J. Lu" To: Uros Bizjak Cc: Jakub Jelinek , Eric Botcazou , gcc-patches@gcc.gnu.org, Richard Henderson Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2012-03/txt/msg01382.txt.bz2 On Tue, Mar 20, 2012 at 11:43 AM, Uros Bizjak wrote: > On Tue, Mar 20, 2012 at 7:27 PM, H.J. Lu wrote: > >>>> I think use the OS provided instruction to load TP into DImode register >>>> could simplify the code. >>> >>> Which OS provided instruction? >>> >>> Please see how TP is defined in get_thread_pointer, it is in ptr_mode: >>> >>> =A0rtx tp =3D gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSP= EC_TP); >>> >>> This says that TP is in SImode on X32. > >> TP is defined as (unspec:DI [(const_int 0]) UNSPEC_TP) >> and provided by OS. =A0It is a CONST_INT, but its value is opaque >> to GCC. MODE here has no impact on its value provided by OS. >> X32 OS provides instructions to load TP to into an SImode and >> DImode registers. > > You must be looking to some other GCC sources than me. > > (define_insn "*load_tp_x32" > =A0[(set (match_operand:SI 0 "register_operand" "=3Dr") > =A0 =A0 =A0 =A0(unspec:SI [(const_int 0)] UNSPEC_TP))] > =A0"TARGET_X32" > =A0"mov{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}" > =A0[(set_attr "type" "imov") > =A0 (set_attr "modrm" "0") > =A0 (set_attr "length" "7") > =A0 (set_attr "memory" "load") > =A0 (set_attr "imm_disp" "false")]) > > (define_insn "*load_tp_x32_zext" > =A0[(set (match_operand:DI 0 "register_operand" "=3Dr") > =A0 =A0 =A0 =A0(zero_extend:DI (unspec:SI [(const_int 0)] UNSPEC_TP)))] > =A0"TARGET_X32" > =A0"mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}" > =A0[(set_attr "type" "imov") > =A0 (set_attr "modrm" "0") > =A0 (set_attr "length" "7") > =A0 (set_attr "memory" "load") > =A0 (set_attr "imm_disp" "false")]) > Thread pointer (TP) points to thread control block (TCB). X32 TCB is typedef struct { void *tcb; /* Pointer to the TCB. Not necessarily the thread descriptor used by libpthread. */ ... } It is a 32bit address set up by OS. That is where 0 in "%fs:0" comes from since it is the first field of the struct %fs points to. X32 OS provi= des mov %fs:0, %eax to load the address of TCB into EAX and mov %fs:0, %eax to load the address of TCB into RAX since OS guarantees that the upper 32bits of the address of TCB are all 0s. We added "*load_tp_x32_zext" since we zero-extend SI TP to DI TP. Or we can use mov %fs:0, %eax to directly load the value of the tcb field into RAX and remove "*load_tp_x32_zext". It will simplify the code. --=20 H.J.