From: "H.J. Lu" <hjl.tools@gmail.com>
To: Richard Biener <richard.guenther@gmail.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
Hongtao Liu <hongtao.liu@intel.com>
Subject: Re: [PATCH] x86: Compile CPUID functions with -mgeneral-regs-only
Date: Thu, 24 Jun 2021 05:41:53 -0700 [thread overview]
Message-ID: <CAMe9rOoCPiFUgV3kC2nxO22SKuE3qPwougH5B_BmzEanN_2OPw@mail.gmail.com> (raw)
In-Reply-To: <CAFiYyc30E0mh=QEoSXFG8Wq7V1=Tea9X-xXBBm8LHhj2KnGz4g@mail.gmail.com>
On Thu, Jun 24, 2021 at 5:35 AM Richard Biener
<richard.guenther@gmail.com> wrote:
>
> On Thu, Jun 24, 2021 at 2:13 PM H.J. Lu via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > CPUID functions are used to detect CPU features. If vector ISAs
> > are enabled, compiler is free to use them in these functions. Add
> > __attribute__ ((target("general-regs-only"))) to CPUID functions
> > to avoid vector instructions.
>
> But there are GPR instructions not in x86_64, so shouldn't
> we use target("march=x86_64") or so? Note doing either will
> of course prevent inlining of those "inlines".
Does -march=x86_64, which enables CMOV and other GPR
ISAs, work for -m32?
> So I'm not sure how much of a fix this is ... the error will almost
> always be visible in the caller as well.
I think _attribute__ ((target("general-regs-only"))) is a step
forward.
> > gcc/
> >
> > PR target/101185
> > * config/i386/cpuid.h (__get_cpuid_max): Add
> > __attribute__ ((target("general-regs-only"))).
> > (__get_cpuid): Likewise.
> > (__get_cpuid_count): Likewise.
> > (__cpuidex): Likewise.
> >
> > gcc/testsuite/
> >
> > PR target/101185
> > * gcc.target/i386/avx512-check.h (check_osxsave): Add
> > __attribute__ ((target("general-regs-only"))).
> > (main): Likewise.
> > ---
> > gcc/config/i386/cpuid.h | 4 ++++
> > gcc/testsuite/gcc.target/i386/avx512-check.h | 2 ++
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
> > index aebc17c6827..74881ee91e5 100644
> > --- a/gcc/config/i386/cpuid.h
> > +++ b/gcc/config/i386/cpuid.h
> > @@ -243,6 +243,7 @@
> > pointer is non-null, then first four bytes of the signature
> > (as found in ebx register) are returned in location pointed by sig. */
> >
> > +__attribute__ ((target("general-regs-only")))
> > static __inline unsigned int
> > __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
> > {
> > @@ -298,6 +299,7 @@ __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
> > supported and returns 1 for valid cpuid information or 0 for
> > unsupported cpuid leaf. All pointers are required to be non-null. */
> >
> > +__attribute__ ((target("general-regs-only")))
> > static __inline int
> > __get_cpuid (unsigned int __leaf,
> > unsigned int *__eax, unsigned int *__ebx,
> > @@ -315,6 +317,7 @@ __get_cpuid (unsigned int __leaf,
> >
> > /* Same as above, but sub-leaf can be specified. */
> >
> > +__attribute__ ((target("general-regs-only")))
> > static __inline int
> > __get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
> > unsigned int *__eax, unsigned int *__ebx,
> > @@ -330,6 +333,7 @@ __get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
> > return 1;
> > }
> >
> > +__attribute__ ((target("general-regs-only")))
> > static __inline void
> > __cpuidex (int __cpuid_info[4], int __leaf, int __subleaf)
> > {
> > diff --git a/gcc/testsuite/gcc.target/i386/avx512-check.h b/gcc/testsuite/gcc.target/i386/avx512-check.h
> > index 0a377dba1d5..406faf8fe03 100644
> > --- a/gcc/testsuite/gcc.target/i386/avx512-check.h
> > +++ b/gcc/testsuite/gcc.target/i386/avx512-check.h
> > @@ -25,6 +25,7 @@ do_test (void)
> > }
> > #endif
> >
> > +__attribute__ ((target("general-regs-only")))
> > static int
> > check_osxsave (void)
> > {
> > @@ -34,6 +35,7 @@ check_osxsave (void)
> > return (ecx & bit_OSXSAVE) != 0;
> > }
> >
> > +__attribute__ ((target("general-regs-only")))
> > int
> > main ()
> > {
> > --
> > 2.31.1
> >
--
H.J.
next prev parent reply other threads:[~2021-06-24 12:42 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 12:12 H.J. Lu
2021-06-24 12:35 ` Richard Biener
2021-06-24 12:41 ` H.J. Lu [this message]
2021-06-24 12:47 ` Richard Biener
2021-06-24 13:00 ` H.J. Lu
2021-06-24 16:12 ` Uros Bizjak
2021-06-24 18:00 ` H.J. Lu
2021-06-25 2:56 ` Hongtao Liu
2021-06-25 7:49 ` Uros Bizjak
2021-06-25 12:39 ` [PATCH v2] x86: Check AVX512 without mask instructions H.J. Lu
2021-07-14 12:27 ` PING^1 " H.J. Lu
2021-07-26 3:33 ` Hongtao Liu
2021-07-30 10:02 ` Uros Bizjak
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