From: "H.J. Lu" <hjl.tools@gmail.com>
To: Uros Bizjak <ubizjak@gmail.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH 00/41] V8: Emulate MMX intrinsics with SSE
Date: Sun, 17 Feb 2019 20:47:00 -0000 [thread overview]
Message-ID: <CAMe9rOoX75MBaG9387Taz0gbwzFRauV2SP6_bSQZ5c7CEbAX_Q@mail.gmail.com> (raw)
In-Reply-To: <CAFULd4b7HWB5-_ByzKWdKv8_H64eMD2tCff5F1FgY7=Ek__b+g@mail.gmail.com>
On Sun, Feb 17, 2019 at 10:49 AM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On Sun, Feb 17, 2019 at 6:37 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> > > > > > > > > On x86-64, since __m64 is returned and passed in XMM registers, we can
> > > > > > > > > emulate MMX intrinsics with SSE instructions. To support it, we added
> > > > > > > > >
> > > > > > > > > #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
> > > > > > > > >
> > > > > > > > > ;; Define instruction set of MMX instructions
> > > > > > > > > (define_attr "mmx_isa" "base,native,x64,x64_noavx,x64_avx"
> > > > > > > > > (const_string "base"))
> > > > > > > > >
> > > > > > > > > (eq_attr "mmx_isa" "native")
> > > > > > > > > (symbol_ref "!TARGET_MMX_WITH_SSE")
> > > > > > > > > (eq_attr "mmx_isa" "x64")
> > > > > > > > > (symbol_ref "TARGET_MMX_WITH_SSE")
> > > > > > > > > (eq_attr "mmx_isa" "x64_avx")
> > > > > > > > > (symbol_ref "TARGET_MMX_WITH_SSE && TARGET_AVX")
> > > > > > > > > (eq_attr "mmx_isa" "x64_noavx")
> > > > > > > > > (symbol_ref "TARGET_MMX_WITH_SSE && !TARGET_AVX")
> > > > > > > > >
> > > > > > > > > We added SSE emulation to MMX patterns and disabled MMX alternatives with
> > > > > > > > > TARGET_MMX_WITH_SSE.
> > > > > > > > >
> > > > > > > > > Most of MMX instructions have equivalent SSE versions and results of some
> > > > > > > > > SSE versions need to be reshuffled to the right order for MMX. Thee are
> > > > > > > > > couple tricky cases:
> > > > > > > > >
> > > > > > > > > 1. MMX maskmovq and SSE2 maskmovdqu aren't equivalent. We emulate MMX
> > > > > > > > > maskmovq with SSE2 maskmovdqu by zeroing out the upper 64 bits of the
> > > > > > > > > mask operand and handle unmapped bits 64:127 at memory address by
> > > > > > > > > adjusting source and mask operands together with memory address.
> > > > > > > > >
> > > > > > > > > 2. MMX movntq is emulated with SSE2 DImode movnti, which is available
> > > > > > > > > in 64-bit mode.
> > > > > > > > >
> > > > > > > > > 3. MMX pshufb takes a 3-bit index while SSE pshufb takes a 4-bit index.
> > > > > > > > > SSE emulation must clear the bit 4 in the shuffle control mask.
> > > > > > > > >
> > > > > > > > > 4. To emulate MMX cvtpi2p with SSE2 cvtdq2ps, we must properly preserve
> > > > > > > > > the upper 64 bits of destination XMM register.
> > > > > > > > >
> > > > > > > > > Tests are also added to check each SSE emulation of MMX intrinsics.
> > > > > > > > >
> > > > > > > > > There are no regressions on i686 and x86-64. For x86-64, GCC is also
> > > > > > > > > tested with
> > > > > > > > >
> > > > > > > > > --with-arch=native --with-cpu=native
> > > > > > > > >
> > > > > > > > > on AVX2 and AVX512F machines.
> > > > > > > >
> > > > > > > > An idea that would take patch a step further also on 32 bit targets:
> > > > > > > >
> > > > > > > > *Assuming* that operations on XMM registers are as fast (or perhaps
> > > > > > > > faster) than operations on MMX registers, we can change mmx_isa
> > > > > > > > attribute in e.g.
> > > > > > > >
> > > > > > > > + "@
> > > > > > > > + p<logic>\t{%2, %0|%0, %2}
> > > > > > > > + p<logic>\t{%2, %0|%0, %2}
> > > > > > > > + vp<logic>\t{%2, %1, %0|%0, %1, %2}"
> > > > > > > > + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> > > > > > > >
> > > > > > > > to:
> > > > > > > >
> > > > > > > > [(set_attr "isa" "*,noavx,avx")
> > > > > > > > (set_attr "mmx_isa" "native,*,*")]
> > > > > > > >
> > > > > > > > So, for x86_64 everything stays the same, but for x86_32 we now allow
> > > > > > > > intrinsics to use xmm registers in addition to mmx registers. We can't
> > > > > > > > disable MMX for x64_32 anyway due to ISA constraints (and some tricky
> > > > > > > > cases, e.g. monvti that works only for 64bit targets and e.g. maskmovq
> > > > > > > > & similar, which are more efficient with MMX regs), but RA has much
> > > > > > > > more freedom to allocate the most effective register set even for
> > > > > > > > 32bit targets.
> > > > > > > >
> > > > > > > > WDYT?
> > > > > > > >
> > > > > > >
> > > > > > > Since MMX registers are used to pass and return __m64 values,
> > > > > > > we can't really get rid of MMX instructions in 32-bit mode. If people
> > > > > > > have to stay with 32-bit mode, they need MMX. I don't think we should
> > > > > > > extend TARGET_MMX_WITH_SSE to 32-bit mode.
> > > > > >
> > > > > > No, TARGET_MMX_WITH_SSE is still enabled only for 64bit targets. We
> > > > > > should not *disable* SSE alternatives on 32bit targets.
> > > >
> > > > I don't think my patch set disables any SSE alternatives in 32-bit
> > > > mode. However,
> > > > it DOES NOT enable any SSE alternatives in 32-bit mode. To really enable SSE
> > > > alternatives in
> > > >
> > > > (define_insn "*mmx_<code><mode>3"
> > > > [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv")
> > > > (any_logic:MMXMODEI
> > > > (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,Yv")
> > > > (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")))]
> > > > "(TARGET_MMX || TARGET_MMX_WITH_SSE)
> > > > && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> > > > "@
> > > > p<logic>\t{%2, %0|%0, %2}
> > > > p<logic>\t{%2, %0|%0, %2}
> > > > vp<logic>\t{%2, %1, %0|%0, %1, %2}"
> > > > [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> > > > (set_attr "type" "mmxadd,sselog,sselog")
> > > > (set_attr "mode" "DI,TI,TI")])
> > > >
> > > > register_mmxmem_operand must return true for SSE alternatives:
> > >
> > > It returns true for register and memory operands for 32bit targets, because
> > >
> > > #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
> >
> > Will
> >
> > (match_operand:V4HI 2 "nonimmediate_operand" "ym,x,Yv"))))]
> >
> > work well with RA? I got some wrong code before register_mmxmem_operand
> > was added to match "ym,x,Yv".
>
> I see no reason why it shouldn't.
This will be equivalent to replace register_operand in
[(match_operand:VI1_AVX512VLBW 1 "register_operand" "v")
with nonimmediate_operand. If it should work, I can do it in i386.md and
sse.md to check it out.
--
H.J.
next prev parent reply other threads:[~2019-02-17 20:47 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-16 22:41 H.J. Lu
2019-02-16 22:40 ` [PATCH 08/41] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 " H.J. Lu
2019-02-16 22:40 ` [PATCH 03/41] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX H.J. Lu
2019-02-16 22:40 ` [PATCH 15/41] i386: Emulate MMX sse_cvtpi2ps with SSE H.J. Lu
2019-02-16 22:40 ` [PATCH 09/41] i386: Emulate MMX <any_logic><mode>3 " H.J. Lu
2019-02-16 22:40 ` [PATCH 01/41] i386: Allow MMX register modes in SSE registers H.J. Lu
2019-02-16 22:40 ` [PATCH 11/41] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE H.J. Lu
2019-02-16 22:40 ` [PATCH 12/41] i386: Emulate MMX vec_dupv2si " H.J. Lu
2019-02-16 22:40 ` [PATCH 06/41] i386: Emulate MMX smulv4hi3_highpart " H.J. Lu
2019-02-16 22:40 ` [PATCH 04/41] i386: Emulate MMX plusminus/sat_plusminus " H.J. Lu
2019-02-16 22:41 ` [PATCH 17/41] i386: Emulate MMX mmx_pinsrw " H.J. Lu
2019-02-16 22:41 ` [PATCH 05/41] i386: Emulate MMX mulv4hi3 " H.J. Lu
2019-02-16 22:41 ` [PATCH 16/41] i386: Emulate MMX mmx_pextrw " H.J. Lu
2019-02-16 22:41 ` [PATCH 14/41] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi " H.J. Lu
2019-02-16 22:41 ` [PATCH 31/41] i386: Emulate MMX ssse3_pmulhrswv4hi3 " H.J. Lu
2019-02-16 22:41 ` [PATCH 02/41] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 H.J. Lu
2019-02-16 22:41 ` [PATCH 27/41] i386: Make _mm_empty () as NOP for TARGET_MMX_WITH_SSE H.J. Lu
2019-02-17 9:45 ` Uros Bizjak
2019-02-17 13:38 ` H.J. Lu
2019-02-16 22:41 ` [PATCH 28/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE H.J. Lu
2019-02-16 22:41 ` [PATCH 40/41] i386: Enable TM MMX intrinsics with SSE2 H.J. Lu
2019-02-16 22:41 ` [PATCH 07/41] i386: Emulate MMX mmx_pmaddwd with SSE H.J. Lu
2019-02-16 22:41 ` [PATCH 25/41] i386: Emulate MMX movntq with SSE2 movntidi H.J. Lu
2019-02-16 22:41 ` [PATCH 10/41] i386: Emulate MMX mmx_andnot<mode>3 with SSE H.J. Lu
2019-02-16 22:41 ` [PATCH 13/41] i386: Emulate MMX pshufw " H.J. Lu
2019-02-16 22:41 ` [PATCH 33/41] i386: Emulate MMX ssse3_psign<mode>3 " H.J. Lu
2019-02-16 22:42 ` [PATCH 41/41] i386: Add tests for MMX intrinsic emulations " H.J. Lu
2019-02-16 22:46 ` [PATCH 19/41] i386: Emulate MMX mmx_pmovmskb " H.J. Lu
2019-02-16 22:46 ` [PATCH 20/41] i386: Emulate MMX mmx_umulv4hi3_highpart " H.J. Lu
2019-02-16 22:47 ` [PATCH 39/41] i386: Allow MMX intrinsic emulation " H.J. Lu
2019-02-16 22:47 ` [PATCH 37/41] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 24/41] i386: Emulate MMX mmx_psadbw with SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 22/41] i386: Emulate MMX mmx_uavgv8qi3 " H.J. Lu
2019-02-16 22:47 ` [PATCH 35/41] i386: Emulate MMX abs<mode>2 " H.J. Lu
2019-02-16 22:47 ` [PATCH 26/41] i386: Emulate MMX umulv1siv1di3 with SSE2 H.J. Lu
2019-02-16 22:47 ` [PATCH 36/41] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-18 12:56 ` Uros Bizjak
2019-02-16 22:47 ` [PATCH 38/41] i386: Allow MMX vector expanders " H.J. Lu
2019-02-17 16:25 ` Uros Bizjak
2019-02-17 17:03 ` H.J. Lu
2019-02-17 17:09 ` Uros Bizjak
2019-02-17 17:15 ` H.J. Lu
2019-02-17 17:22 ` Uros Bizjak
2019-02-17 17:28 ` H.J. Lu
2019-02-17 18:50 ` Uros Bizjak
2019-02-17 20:49 ` H.J. Lu
2019-02-16 22:47 ` [PATCH 18/41] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 23/41] i386: Emulate MMX mmx_uavgv4hi3 " H.J. Lu
2019-02-16 22:47 ` [PATCH 30/41] i386: Emulate MMX ssse3_pmaddubsw " H.J. Lu
2019-02-16 22:47 ` [PATCH 32/41] i386: Emulate MMX pshufb with SSE version H.J. Lu
2019-02-16 22:47 ` [PATCH 34/41] i386: Emulate MMX ssse3_palignrdi with SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 21/41] i386: Emulate MMX maskmovq with SSE2 maskmovdqu H.J. Lu
2019-02-16 22:47 ` [PATCH 29/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE H.J. Lu
2019-02-17 10:33 ` [PATCH 00/41] V8: Emulate MMX intrinsics " Uros Bizjak
2019-02-17 13:42 ` H.J. Lu
2019-02-17 15:54 ` Uros Bizjak
2019-02-17 15:57 ` Uros Bizjak
2019-02-17 17:10 ` H.J. Lu
2019-02-17 17:27 ` Uros Bizjak
2019-02-17 17:37 ` H.J. Lu
2019-02-17 18:49 ` Uros Bizjak
2019-02-17 20:47 ` H.J. Lu [this message]
2019-02-18 14:22 ` H.J. Lu
2019-02-18 14:37 ` Uros Bizjak
2019-02-18 14:48 ` H.J. Lu
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