From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 111070 invoked by alias); 30 Apr 2015 15:18:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 111013 invoked by uid 89); 30 Apr 2015 15:18:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f175.google.com Received: from mail-ob0-f175.google.com (HELO mail-ob0-f175.google.com) (209.85.214.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 30 Apr 2015 15:18:04 +0000 Received: by obbeb7 with SMTP id eb7so46723187obb.3 for ; Thu, 30 Apr 2015 08:18:02 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.182.97.138 with SMTP id ea10mr1520987obb.11.1430407082814; Thu, 30 Apr 2015 08:18:02 -0700 (PDT) Received: by 10.76.54.14 with HTTP; Thu, 30 Apr 2015 08:18:02 -0700 (PDT) In-Reply-To: <20150430151512.GA106194@msticlxl7.ims.intel.com> References: <20150319092404.GA73948@msticlxl7.ims.intel.com> <20150323160222.GB10265@msticlxl7.ims.intel.com> <20150324134311.GA40649@msticlxl57.ims.intel.com> <20150428162049.GA62528@msticlxl7.ims.intel.com> <20150430151512.GA106194@msticlxl7.ims.intel.com> Date: Thu, 30 Apr 2015 15:22:00 -0000 Message-ID: Subject: Re: [PATCH, PR65915] Fix float conversion split. From: "H.J. Lu" To: Ilya Tocar Cc: Kirill Yukhin , GCC Patches , Uros Bizjak Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg02049.txt.bz2 On Thu, Apr 30, 2015 at 8:15 AM, Ilya Tocar wrote: >> Hi, >> >> Looks like I missed some splits, which caused PR65915. >> Patch below fixes it. >> Ok for trunk? >> >> 2015-04-28 Ilya Tocar >> >> * config/i386/i386.md (define_split): Check for xmm16+, >> when splitting scalar float conversion. >> >> >> --- >> gcc/config/i386/i386.md | 8 ++++++-- >> 1 file changed, 6 insertions(+), 2 deletions(-) >> >> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md >> index 937871a..af1cd9b 100644 >> --- a/gcc/config/i386/i386.md >> +++ b/gcc/config/i386/i386.md >> @@ -4897,7 +4897,9 @@ >> "TARGET_SSE2 && TARGET_SSE_MATH >> && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) >> && reload_completed && SSE_REG_P (operands[0]) >> - && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)" >> + && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC) >> + && (!EXT_REX_SSE_REG_P (operands[0]) >> + || TARGET_AVX512VL)" >> [(const_int 0)] >> { >> operands[3] = simplify_gen_subreg (mode, operands[0], >> @@ -4921,7 +4923,9 @@ >> "TARGET_SSE2 && TARGET_SSE_MATH >> && TARGET_SSE_PARTIAL_REG_DEPENDENCY >> && optimize_function_for_speed_p (cfun) >> - && reload_completed && SSE_REG_P (operands[0])" >> + && reload_completed && SSE_REG_P (operands[0]) >> + && (!EXT_REX_SSE_REG_P (operands[0]) >> + || TARGET_AVX512VL)" >> [(const_int 0)] >> { >> const machine_mode vmode = mode; >> -- >> 1.8.3.1 >> > > Updated version below (now with test). > > --- > gcc/config/i386/i386.md | 8 ++++++-- > gcc/config/i386/sse.md | 6 +++--- > gcc/testsuite/gcc.target/i386/pr65915.c | 6 ++++++ > 3 files changed, 15 insertions(+), 5 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr65915.c > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index 937871a..af1cd9b 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -4897,7 +4897,9 @@ > "TARGET_SSE2 && TARGET_SSE_MATH > && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) > && reload_completed && SSE_REG_P (operands[0]) > - && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)" > + && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC) > + && (!EXT_REX_SSE_REG_P (operands[0]) > + || TARGET_AVX512VL)" > [(const_int 0)] > { > operands[3] = simplify_gen_subreg (mode, operands[0], > @@ -4921,7 +4923,9 @@ > "TARGET_SSE2 && TARGET_SSE_MATH > && TARGET_SSE_PARTIAL_REG_DEPENDENCY > && optimize_function_for_speed_p (cfun) > - && reload_completed && SSE_REG_P (operands[0])" > + && reload_completed && SSE_REG_P (operands[0]) > + && (!EXT_REX_SSE_REG_P (operands[0]) > + || TARGET_AVX512VL)" > [(const_int 0)] > { > const machine_mode vmode = mode; > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 9b7009a..c61098d 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -4258,11 +4258,11 @@ > (set_attr "mode" "TI")]) > > (define_insn "sse2_cvtsi2sd" > - [(set (match_operand:V2DF 0 "register_operand" "=x,x,x") > + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v") > (vec_merge:V2DF > (vec_duplicate:V2DF > (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm"))) > - (match_operand:V2DF 1 "register_operand" "0,0,x") > + (match_operand:V2DF 1 "register_operand" "0,0,v") > (const_int 1)))] > "TARGET_SSE2" > "@ > @@ -4275,7 +4275,7 @@ > (set_attr "amdfam10_decode" "vector,double,*") > (set_attr "bdver1_decode" "double,direct,*") > (set_attr "btver2_decode" "double,double,double") > - (set_attr "prefix" "orig,orig,vex") > + (set_attr "prefix" "orig,orig,maybe_evex") > (set_attr "mode" "DF")]) > > (define_insn "sse2_cvtsi2sdq" > diff --git a/gcc/testsuite/gcc.target/i386/pr65915.c b/gcc/testsuite/gcc.target/i386/pr65915.c > new file mode 100644 > index 0000000..990c5aa > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr65915.c > @@ -0,0 +1,6 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -mavx512f -fpic -mcmodel=medium" } */ > +/* { dg-require-effective-target avx512f } */ > +/* { dg-require-effective-target lp64 } */ > + > +#include "avx512f-vrndscalepd-2.c" Missing testcases for FAIL: gcc.target/i386/avx512f-vrndscaleps-2.c (test for excess errors) FAIL: gcc.target/i386/avx512vl-vrndscaleps-2.c (internal compiler error) as well as ChangeLog entries. -- H.J.