Re: [RFC, PR target/65105] Use vector instructions for scalar 64bit computations on 32bit target

["H.J. Lu" <hjl.tools@gmail.com>]

On Wed, Sep 23, 2015 at 3:29 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Wed, Sep 23, 2015 at 12:19 PM, Ilya Enkovich <enkovich.gnu@gmail.com> wrote:
>> On 14 Sep 17:50, Uros Bizjak wrote:
>>>
>>> +(define_insn_and_split "*zext<mode>_doubleword"
>>> +  [(set (match_operand:DI 0 "register_operand" "=r")
>>> + (zero_extend:DI (match_operand:SWI24 1 "nonimmediate_operand" "rm")))]
>>> +  "!TARGET_64BIT && TARGET_STV && TARGET_SSE2"
>>> +  "#"
>>> +  "&& reload_completed && GENERAL_REG_P (operands[0])"
>>> +  [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
>>> +   (set (match_dup 2) (const_int 0))]
>>> +  "split_double_mode (DImode, &operands[0], 1, &operands[0], &operands[2]);")
>>> +
>>> +(define_insn_and_split "*zextqi_doubleword"
>>> +  [(set (match_operand:DI 0 "register_operand" "=r")
>>> + (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
>>> +  "!TARGET_64BIT && TARGET_STV && TARGET_SSE2"
>>> +  "#"
>>> +  "&& reload_completed && GENERAL_REG_P (operands[0])"
>>> +  [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
>>> +   (set (match_dup 2) (const_int 0))]
>>> +  "split_double_mode (DImode, &operands[0], 1, &operands[0], &operands[2]);")
>>> +
>>>
>>> Please put the above patterns together with other zero_extend
>>> patterns. You can also merge these two patterns using SWI124 mode
>>> iterator with <r> mode attribute as a register constraint. Also, no
>>> need to check for GENERAL_REG_P after reload, when "r" constraint is
>>> in effect:
>>>
>>> (define_insn_and_split "*zext<mode>_doubleword"
>>>   [(set (match_operand:DI 0 "register_operand" "=r")
>>>  (zero_extend:DI (match_operand:SWI124 1 "nonimmediate_operand" "<r>m")))]
>>>   "!TARGET_64BIT && TARGET_STV && TARGET_SSE2"
>>>   "#"
>>>   "&& reload_completed"
>>>   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
>>>    (set (match_dup 2) (const_int 0))]
>>>   "split_double_mode (DImode, &operands[0], 1, &operands[0], &operands[2]);")
>>
>> Register constraint doesn't affect split and I need GENERAL_REG_P to filter other registers case.
>
> OK.
>
>> I merged QI and HI cases of zext but made a separate pattern for SI case because it doesn't need zero_extend in resulting code.  Bootstrapped and regtested for x86_64-unknown-linux-gnu.
>
> This change is OK.
>
> The patch LGTM, but please wait a couple of days if Jeff has some
> comment on algorithmic aspect of the patch.
>
> Thanks,
> Uros.
>
>>
>> Thanks,
>> Ilya
>> --
>> gcc/
>>
>> 2015-09-23  Ilya Enkovich  <enkovich.gnu@gmail.com>
>>
>>         * config/i386/i386.c: Include dbgcnt.h.
>>         (has_non_address_hard_reg): New.
>>         (convertible_comparison_p): New.
>>         (scalar_to_vector_candidate_p): New.
>>         (remove_non_convertible_regs): New.
>>         (scalar_chain): New.
>>         (scalar_chain::scalar_chain): New.
>>         (scalar_chain::~scalar_chain): New.
>>         (scalar_chain::add_to_queue): New.
>>         (scalar_chain::mark_dual_mode_def): New.
>>         (scalar_chain::analyze_register_chain): New.
>>         (scalar_chain::add_insn): New.
>>         (scalar_chain::build): New.
>>         (scalar_chain::compute_convert_gain): New.
>>         (scalar_chain::replace_with_subreg): New.
>>         (scalar_chain::replace_with_subreg_in_insn): New.
>>         (scalar_chain::emit_conversion_insns): New.
>>         (scalar_chain::make_vector_copies): New.
>>         (scalar_chain::convert_reg): New.
>>         (scalar_chain::convert_op): New.
>>         (scalar_chain::convert_insn): New.
>>         (scalar_chain::convert): New.
>>         (convert_scalars_to_vector): New.
>>         (pass_data_stv): New.
>>         (pass_stv): New.
>>         (make_pass_stv): New.
>>         (ix86_option_override): Created and register stv pass.
>>         (flag_opts): Add -mstv.
>>         (ix86_option_override_internal): Likewise.
>>         * config/i386/i386.md (SWIM1248x): New.
>>         (*movdi_internal): Add xmm to mem alternative for TARGET_STV.
>>         (and<mode>3): Use SWIM1248x iterator instead of SWIM.
>>         (*anddi3_doubleword): New.
>>         (*zext<mode>_doubleword): New.
>>         (*zextsi_doubleword): New.
>>         (<code><mode>3): Use SWIM1248x iterator instead of SWIM.
>>         (*<code>di3_doubleword): New.
>>         * config/i386/i386.opt (mstv): New.
>>         * dbgcnt.def (stv_conversion): New.
>>

This caused:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67761



-- 
H.J.