From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 89214 invoked by alias); 18 Dec 2015 16:52:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 88241 invoked by uid 89); 18 Dec 2015 16:52:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,KAM_ASCII_DIVIDERS,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=no version=3.3.2 spammy=231819, enkovich.gnu@gmail.com, enkovichgnugmailcom, Hx-languages-length:1931 X-HELO: mail-qk0-f170.google.com Received: from mail-qk0-f170.google.com (HELO mail-qk0-f170.google.com) (209.85.220.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 18 Dec 2015 16:52:46 +0000 Received: by mail-qk0-f170.google.com with SMTP id u65so94353545qkh.2 for ; Fri, 18 Dec 2015 08:52:45 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.55.79.195 with SMTP id d186mr6387715qkb.62.1450457563787; Fri, 18 Dec 2015 08:52:43 -0800 (PST) Received: by 10.55.181.70 with HTTP; Fri, 18 Dec 2015 08:52:43 -0800 (PST) In-Reply-To: <20151112120340.GB51435@msticlxl57.ims.intel.com> References: <20151112120340.GB51435@msticlxl57.ims.intel.com> Date: Fri, 18 Dec 2015 16:52:00 -0000 Message-ID: Subject: Re: [PATCH, PR tree-optimization/PR68305] Support masked COND_EXPR in SLP From: "H.J. Lu" To: Ilya Enkovich Cc: GCC Patches Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2015-12/txt/msg01895.txt.bz2 On Thu, Nov 12, 2015 at 4:03 AM, Ilya Enkovich wrote: > Hi, > > This patch fixes a way operand is chosen by its num for COND_EXPR. Bootstrapped and regtested on x86_64-unknown-linux-gnu. OK for trunk? > > Thanks, > Ilya > -- > gcc/ > > 2015-11-12 Ilya Enkovich > > PR tree-optimization/68305 > * tree-vect-slp.c (vect_get_constant_vectors): Support > COND_EXPR with SSA_NAME as a condition. > > gcc/testsuite/ > > 2015-11-12 Ilya Enkovich > > PR tree-optimization/68305 > * gcc.dg/vect/pr68305.c: New test. > > > diff --git a/gcc/testsuite/gcc.dg/vect/pr68305.c b/gcc/testsuite/gcc.dg/vect/pr68305.c > new file mode 100644 > index 0000000..fde3db7 > --- /dev/null > +++ b/gcc/testsuite/gcc.dg/vect/pr68305.c > @@ -0,0 +1,13 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-O3" } */ > +/* { dg-additional-options "-mavx2" { target avx_runtime } } */ > + > Since this is a compile test, there is no need for AVX run-time. I checked in this as an obvious fix. -- H.J. --- Index: ChangeLog =================================================================== --- ChangeLog (revision 231819) +++ ChangeLog (working copy) @@ -1,3 +1,8 @@ +2015-12-18 H.J. Lu + + * gcc.dg/vect/pr68305.c (dg-additional-options): Add -mavx2 + for x86 target. + 2015-12-18 Nathan Sidwell * c-c++-common/attr-simd-3.c: Requires pthreads. Index: gcc.dg/vect/pr68305.c =================================================================== --- gcc.dg/vect/pr68305.c (revision 231819) +++ gcc.dg/vect/pr68305.c (working copy) @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-additional-options "-O3" } */ -/* { dg-additional-options "-mavx2" { target avx_runtime } } */ +/* { dg-additional-options "-mavx2" { target { i?86-*-* x86_64-*-* } } } */ int a, b;