From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 96112 invoked by alias); 1 Oct 2018 12:45:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 95901 invoked by uid 89); 1 Oct 2018 12:45:31 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Received:sk:j4-v6mr X-HELO: mail-ot1-f65.google.com Received: from mail-ot1-f65.google.com (HELO mail-ot1-f65.google.com) (209.85.210.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 01 Oct 2018 12:45:30 +0000 Received: by mail-ot1-f65.google.com with SMTP id u22so2364172ota.12 for ; Mon, 01 Oct 2018 05:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=CQSQbo9mHWFiBrqzSotb/eG4fi3tVXmwrHy4V2VGOYs=; b=vYlqX4C5ux1My0nVIcdPW6ajmTVEMQiVf36i3B/QiTL0xEh0E2cxarRFayjZZHAvI6 ZYPaPJO6Dv9lWLAfOOIvXVnRiHY2f+TCz8lJYtJvQUz6fHANkWlOrUMTXU0/BNfjw1LD vIHZadAm9n19huP1HpIG3cMwcU+5sC8IyNs7fCFt0rsuwiZxUV3p5dSIgQso5FQLsj6Z 0am/dZqisRLzwnGuml/8htcG39I/4vFtPb/Zq9mPNugDFK6QHEjAWVqf+Kaut//IadV3 FL8h4l0WAimbMqJMex/uHSetqUqXPWGug0dDsxG4wmJ/nFsJxdkS7jb9LUFYHQq/qsry 7Q7w== MIME-Version: 1.0 References: <616affd5-5140-8e15-9081-1635f7d4e700@redhat.com> <6ff45a7e-2415-2d18-1d53-5a50964a2174@linux.ibm.com> In-Reply-To: <6ff45a7e-2415-2d18-1d53-5a50964a2174@linux.ibm.com> From: "H.J. Lu" Date: Mon, 01 Oct 2018 12:46:00 -0000 Message-ID: Subject: Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register To: bergner@linux.ibm.com Cc: Vladimir Makarov , GCC Patches , Jeffrey Law Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2018-10/txt/msg00023.txt.bz2 On Sun, Sep 30, 2018 at 6:18 PM Peter Bergner wrote: > > On 9/30/18 7:57 PM, H.J. Lu wrote: > > This caused: > > > > FAIL: gcc.target/i386/pr63527.c scan-assembler-not movl[ \t]%[^,]+, %ebx > > FAIL: gcc.target/i386/pr63534.c scan-assembler-not movl[ \t]%[^,]+, %ebx > > FAIL: gcc.target/i386/pr64317.c scan-assembler addl[ > > \\t]+[$]_GLOBAL_OFFSET_TABLE_, %ebx > > FAIL: gcc.target/i386/pr64317.c scan-assembler movl[ \\t]+c@GOTOFF[(]%ebx[)] > > Can you check whether the new generated code is at least as good > as the old generated code? I'm assuming the code we generate now isn't > wrong, just different and maybe we just need to change what we expect > to see. I checked gcc.target/i386/pr63527.c and it has a regression. Before: 00000000 : 0: 53 push %ebx 1: e8 fc ff ff ff call 2 6: 81 c3 02 00 00 00 add $0x2,%ebx c: 83 ec 08 sub $0x8,%esp f: e8 fc ff ff ff call 10 14: e8 fc ff ff ff call 15 19: 83 c4 08 add $0x8,%esp 1c: 5b pop %ebx 1d: c3 ret Disassembly of section .text.__x86.get_pc_thunk.bx: 00000000 <__x86.get_pc_thunk.bx>: 0: 8b 1c 24 mov (%esp),%ebx 3: c3 ret After: 00000000 : 0: 56 push %esi 1: e8 fc ff ff ff call 2 6: 81 c6 02 00 00 00 add $0x2,%esi c: 53 push %ebx d: 83 ec 04 sub $0x4,%esp 10: 89 f3 mov %esi,%ebx 12: e8 fc ff ff ff call 13 17: e8 fc ff ff ff call 18 1c: 83 c4 04 add $0x4,%esp 1f: 5b pop %ebx 20: 5e pop %esi 21: c3 ret Disassembly of section .text.__x86.get_pc_thunk.si: 00000000 <__x86.get_pc_thunk.si>: 0: 8b 34 24 mov (%esp),%esi 3: c3 ret -- H.J.