From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 57567 invoked by alias); 20 Jan 2019 18:18:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 57534 invoked by uid 89); 20 Jan 2019 18:18:34 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS,TIME_LIMIT_EXCEEDED autolearn=unavailable version=3.3.2 spammy=click, website X-HELO: mail-oi1-f196.google.com Received: from mail-oi1-f196.google.com (HELO mail-oi1-f196.google.com) (209.85.167.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 20 Jan 2019 18:18:24 +0000 Received: by mail-oi1-f196.google.com with SMTP id a77so12853932oii.5 for ; Sun, 20 Jan 2019 10:18:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=t9NKuIC1ltioGiQCai1EaK4PArgxndLNoziTYWSkliM=; b=UImvgVcFNBCKSCMWuYf9Wsd5qXgGQ8nOSPnP388UsFORdbgP28aeD5/E993ZBVrhI6 /mfso8wxR8nPyHKk59w55HT/zSqws/b3gQJ2j1k4/DdZQxmBJMiu5PkACuz0k4ri4omD 0v69UjEZkoa3ORkv5OQ3juWAI42bPujTW5YNdvfE6Lli0nRxNexe99PVnQiBNtYLwos9 IMvO7/3lXmP5dEHFAyAyExA1P3vcevY/O68PSMncZCgyWCBMfu80fopr2PUMHTYPCf/r 7rL5lgO8KaLUSpl/wk0eKbm7LsPXqHDK7VTJR8kmVFX213VZYtuMGCh7n5TSlcH3jtfI bfSw== MIME-Version: 1.0 References: <20190119160233.GA27159@gmail.com> In-Reply-To: From: "H.J. Lu" Date: Sun, 20 Jan 2019 18:18:00 -0000 Message-ID: Subject: Re: [PATCH] i386: Move Intel intrinsics head files to To: Uros Bizjak Cc: Richard Biener , GCC Patches Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2019-01/txt/msg01157.txt.bz2 On Sun, Jan 20, 2019 at 10:12 AM Uros Bizjak wrote: > > On Sun, Jan 20, 2019 at 7:09 PM Uros Bizjak wrote: > > > > On Sun, Jan 20, 2019 at 4:11 PM H.J. Lu wrote: > > > > > > On Sun, Jan 20, 2019 at 4:03 AM Uros Bizjak wrote: > > > > > > > > On 1/19/19, H.J. Lu wrote: > > > > > According to Intel Intrinsics Guide: > > > > > > > > > > https://software.intel.com/sites/landingpage/IntrinsicsGuide/ > > > > > > > > > > Intel intrinsics should be available by including . This > > > > > patch moves remaining Intel intrinsics head files from to > > > > > . > > > > > > > > I can't find the quoted requirement in the provided link. > > > > > > That is an interactive website. If you type in "_xgetbv" and click on it, > > > you will get > > > > > > Synopsis > > > > > > unsigned __int64 _xgetbv (unsigned int a) > > > #include > > > Instruction: xgetbv > > > CPUID Flags: XSAVE > > > > > > Description > > > > > > Copy up to 64-bits from the value of the extended control register > > > (XCR) specified by a into dst. Currently only XFEATURE_ENABLED_MASK > > > XCR is supported. > > > > > > Operation > > > > > > dst[63:0] := XCR[a] > > > > Ah, thanks for the hint. LGTM, but still needs RM approval. > > I wonder, what is/was the purpose of x86intrin.h, considering that > everything can be included from immintrin.h? Some intrinsics aren't covered by Intel Intrinsics Guide, like AMD specific ones. -- H.J.