* [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
@ 2011-10-19 13:50 Kirill Yukhin
2011-10-19 14:38 ` Uros Bizjak
0 siblings, 1 reply; 8+ messages in thread
From: Kirill Yukhin @ 2011-10-19 13:50 UTC (permalink / raw)
To: Uros Bizjak, H.J. Lu, gcc-patches List
[-- Attachment #1: Type: text/plain, Size: 416 bytes --]
Hi,
Here is (almost obvous) patch, which fixes PR50766.
ChangeLog entry:
2011-10-19 Kirill Yukhin <kirill.yukhin@intel.com>
* config/i386/i386.md (bmi_bextr_<mode>): Update register/
memory operand order.
(bmi2_bzhi_<mode>3): Ditto.
(bmi2_pdep_<mode>3): Ditto.
(bmi2_pext_<mode>3): Ditto.
Bootstrapped, test (from bug) passing.
Could you please have a look?
Thanks, K
[-- Attachment #2: pr50766.gcc.patch --]
[-- Type: application/octet-stream, Size: 2169 bytes --]
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 9c9508d..866fb05 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -12099,8 +12099,8 @@
(define_insn "bmi_bextr_<mode>"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
- (match_operand:SWI48 2 "register_operand" "r")]
+ (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_BEXTR))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI"
@@ -12149,9 +12149,9 @@
;; BMI2 instructions.
(define_insn "bmi2_bzhi_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (and:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+ (and:SWI48 (match_operand:SWI48 1 "register_operand" "r")
(lshiftrt:SWI48 (const_int -1)
- (match_operand:SWI48 2 "register_operand" "r"))))
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2"
"bzhi\t{%2, %1, %0|%0, %1, %2}"
@@ -12161,8 +12161,8 @@
(define_insn "bmi2_pdep_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
- (match_operand:SWI48 2 "register_operand" "r")]
+ (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_PDEP))]
"TARGET_BMI2"
"pdep\t{%2, %1, %0|%0, %1, %2}"
@@ -12172,8 +12172,8 @@
(define_insn "bmi2_pext_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
- (match_operand:SWI48 2 "register_operand" "r")]
+ (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_PEXT))]
"TARGET_BMI2"
"pext\t{%2, %1, %0|%0, %1, %2}"
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
2011-10-19 13:50 [PATCH, i386, PR50766] Fix incorrect mem/reg operands order Kirill Yukhin
@ 2011-10-19 14:38 ` Uros Bizjak
2011-10-19 16:34 ` H.J. Lu
0 siblings, 1 reply; 8+ messages in thread
From: Uros Bizjak @ 2011-10-19 14:38 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: H.J. Lu, gcc-patches List
On Wed, Oct 19, 2011 at 3:07 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Here is (almost obvous) patch, which fixes PR50766.
>
> ChangeLog entry:
> 2011-10-19 Kirill Yukhin <kirill.yukhin@intel.com>
>
> * config/i386/i386.md (bmi_bextr_<mode>): Update register/
> memory operand order.
> (bmi2_bzhi_<mode>3): Ditto.
> (bmi2_pdep_<mode>3): Ditto.
> (bmi2_pext_<mode>3): Ditto.
>
> Bootstrapped, test (from bug) passing.
>
> Could you please have a look?
Please also add the testcase from the PR. You can use { dg-do
assemble }, but you have to check for BMI2 effective target support.
BTW: I can't find BMI2 instruction reference documentation, so I'm
just rubberstamping the patch as obvious.
So, OK with the testcase.
Thanks,
Uros.
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
2011-10-19 14:38 ` Uros Bizjak
@ 2011-10-19 16:34 ` H.J. Lu
2011-10-20 7:36 ` Kirill Yukhin
0 siblings, 1 reply; 8+ messages in thread
From: H.J. Lu @ 2011-10-19 16:34 UTC (permalink / raw)
To: Uros Bizjak; +Cc: Kirill Yukhin, gcc-patches List
On Wed, Oct 19, 2011 at 6:21 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Wed, Oct 19, 2011 at 3:07 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
>
>> Here is (almost obvous) patch, which fixes PR50766.
>>
>> ChangeLog entry:
>> 2011-10-19 Kirill Yukhin <kirill.yukhin@intel.com>
>>
>> * config/i386/i386.md (bmi_bextr_<mode>): Update register/
>> memory operand order.
>> (bmi2_bzhi_<mode>3): Ditto.
>> (bmi2_pdep_<mode>3): Ditto.
>> (bmi2_pext_<mode>3): Ditto.
Please mention PR #.
>> Bootstrapped, test (from bug) passing.
>>
>> Could you please have a look?
>
> Please also add the testcase from the PR. You can use { dg-do
> assemble }, but you have to check for BMI2 effective target support.
>
> BTW: I can't find BMI2 instruction reference documentation, so I'm
It is in Intel AVX spec:
http://software.intel.com/en-us/avx/
> just rubberstamping the patch as obvious.
>
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
2011-10-19 16:34 ` H.J. Lu
@ 2011-10-20 7:36 ` Kirill Yukhin
2011-10-20 7:43 ` Uros Bizjak
0 siblings, 1 reply; 8+ messages in thread
From: Kirill Yukhin @ 2011-10-20 7:36 UTC (permalink / raw)
To: H.J. Lu; +Cc: Uros Bizjak, gcc-patches List
[-- Attachment #1: Type: text/plain, Size: 583 bytes --]
Thank you guys,
Updated patch is attached. Test fails wihout and passing with the fix.
ChangeLog entry:
2011-10-20 Kirill Yukhin <kirill.yukhin@intel.com>
PR target/50766
* config/i386/i386.md (bmi_bextr_<mode>): Update register/
memory operand order.
(bmi2_bzhi_<mode>3): Ditto.
(bmi2_pdep_<mode>3): Ditto.
(bmi2_pext_<mode>3): Ditto.
testsuite/ChangeLog entry:
2011-10-20 Kirill Yukhin <kirill.yukhin@intel.com>
PR target/50766
* gcc.target/i386/pr50766.c: New test.
Could you please have a look?
Thanks, K
[-- Attachment #2: pr50766-2.gcc.patch --]
[-- Type: application/octet-stream, Size: 2654 bytes --]
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 9c9508d..866fb05 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -12099,8 +12099,8 @@
(define_insn "bmi_bextr_<mode>"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
- (match_operand:SWI48 2 "register_operand" "r")]
+ (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_BEXTR))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI"
@@ -12149,9 +12149,9 @@
;; BMI2 instructions.
(define_insn "bmi2_bzhi_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (and:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+ (and:SWI48 (match_operand:SWI48 1 "register_operand" "r")
(lshiftrt:SWI48 (const_int -1)
- (match_operand:SWI48 2 "register_operand" "r"))))
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2"
"bzhi\t{%2, %1, %0|%0, %1, %2}"
@@ -12161,8 +12161,8 @@
(define_insn "bmi2_pdep_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
- (match_operand:SWI48 2 "register_operand" "r")]
+ (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_PDEP))]
"TARGET_BMI2"
"pdep\t{%2, %1, %0|%0, %1, %2}"
@@ -12172,8 +12172,8 @@
(define_insn "bmi2_pext_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
- (match_operand:SWI48 2 "register_operand" "r")]
+ (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_PEXT))]
"TARGET_BMI2"
"pext\t{%2, %1, %0|%0, %1, %2}"
diff --git a/gcc/testsuite/gcc.target/i386/pr50766.c b/gcc/testsuite/gcc.target/i386/pr50766.c
new file mode 100644
index 0000000..9923de4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr50766.c
@@ -0,0 +1,17 @@
+/* PR target/50766 */
+/* { dg-do assemble } */
+/* { dg-options "-mbmi2" } */
+/* { dg-require-effective-target bmi2 } */
+
+#include <x86intrin.h>
+
+unsigned z;
+
+void
+foo ()
+{
+ unsigned x = 0x23593464;
+ unsigned y = 0xF9494302;
+ z = _pext_u32(x, y);
+}
+
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
2011-10-20 7:36 ` Kirill Yukhin
@ 2011-10-20 7:43 ` Uros Bizjak
2011-10-20 8:36 ` Kirill Yukhin
0 siblings, 1 reply; 8+ messages in thread
From: Uros Bizjak @ 2011-10-20 7:43 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: H.J. Lu, gcc-patches List
On Thu, Oct 20, 2011 at 6:39 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Updated patch is attached. Test fails wihout and passing with the fix.
>
> ChangeLog entry:
> 2011-10-20 Kirill Yukhin <kirill.yukhin@intel.com>
>
> PR target/50766
> * config/i386/i386.md (bmi_bextr_<mode>): Update register/
> memory operand order.
> (bmi2_bzhi_<mode>3): Ditto.
> (bmi2_pdep_<mode>3): Ditto.
> (bmi2_pext_<mode>3): Ditto.
>
> testsuite/ChangeLog entry:
> 2011-10-20 Kirill Yukhin <kirill.yukhin@intel.com>
>
> PR target/50766
> * gcc.target/i386/pr50766.c: New test.
>
> Could you please have a look?
OK.
Thanks,
Uros.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
2011-10-20 7:43 ` Uros Bizjak
@ 2011-10-20 8:36 ` Kirill Yukhin
2011-10-20 21:04 ` H.J. Lu
0 siblings, 1 reply; 8+ messages in thread
From: Kirill Yukhin @ 2011-10-20 8:36 UTC (permalink / raw)
To: Uros Bizjak; +Cc: H.J. Lu, gcc-patches List
>
> OK.
>
> Thanks,
> Uros.
Great,
could anybody please commit that?
K
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
2011-10-20 8:36 ` Kirill Yukhin
@ 2011-10-20 21:04 ` H.J. Lu
2011-10-21 5:53 ` Kirill Yukhin
0 siblings, 1 reply; 8+ messages in thread
From: H.J. Lu @ 2011-10-20 21:04 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Uros Bizjak, gcc-patches List
On Thu, Oct 20, 2011 at 1:30 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
>>
>> OK.
>>
>> Thanks,
>> Uros.
>
> Great,
> could anybody please commit that?
>
I checked it in for you.
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
2011-10-20 21:04 ` H.J. Lu
@ 2011-10-21 5:53 ` Kirill Yukhin
0 siblings, 0 replies; 8+ messages in thread
From: Kirill Yukhin @ 2011-10-21 5:53 UTC (permalink / raw)
To: H.J. Lu; +Cc: Uros Bizjak, gcc-patches List
Thanks!
K
On Fri, Oct 21, 2011 at 12:37 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Oct 20, 2011 at 1:30 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
>>>
>>> OK.
>>>
>>> Thanks,
>>> Uros.
>>
>> Great,
>> could anybody please commit that?
>>
>
> I checked it in for you.
>
> --
> H.J.
>
^ permalink raw reply [flat|nested] 8+ messages in thread
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2011-10-19 13:50 [PATCH, i386, PR50766] Fix incorrect mem/reg operands order Kirill Yukhin
2011-10-19 14:38 ` Uros Bizjak
2011-10-19 16:34 ` H.J. Lu
2011-10-20 7:36 ` Kirill Yukhin
2011-10-20 7:43 ` Uros Bizjak
2011-10-20 8:36 ` Kirill Yukhin
2011-10-20 21:04 ` H.J. Lu
2011-10-21 5:53 ` Kirill Yukhin
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