From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id 76F933853C0D for ; Thu, 12 Aug 2021 15:26:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 76F933853C0D Received: by mail-pl1-x62a.google.com with SMTP id q2so7730877plr.11 for ; Thu, 12 Aug 2021 08:26:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=eiiaZyS77RBHfRhbEryy5arsrK/Zm9MgH4fkmq9mQhw=; b=TZc9ihabN4qhTLl/h+0PkgrlzG5DDpZaMXWvEF0/Dcn0I6IU6TIFfPiWK5qCwtWFbS LQtKPgAhmWbMvVH9pfEEK9d/KddYkmYtyczvyeYaaw+pE0CTe4UmERlXbYnAxbv3n2Fh lVc61oOXOQGGs3viXKUFKma1iGrAfqq2Ai77pSEyVRyK0WXYoZDS1ElvHhkH+skBcZJU 3NDYHlYsIHZrVFy3QWg6dTph8PPe0ffa+HuCs842Jo337UYSMmydl3n1P+WXRIi/bXGX VvdTf6/8eYGCR5s2cYPMewrbdOBxj7LeQikPoVaz/FicfDvwUauUUcCnm4BQB9vyQm4K pRBQ== X-Gm-Message-State: AOAM5305ussTPHmLX1BYSGJnWlu0pljps1j2A+uPe6Ol9qvZaLMkRs0p usiobKeaQibVIKgkIih85bWRSRdaotRmeVSgQ6E= X-Google-Smtp-Source: ABdhPJzfQROkq+47WkLcJ7gIE+Kti+UftKah68BnGVeUC+FgdpcPnVZe1faNtXjBESXwulN99R1faWsmBnqIbgmtgDw= X-Received: by 2002:a17:90b:30d0:: with SMTP id hi16mr2993316pjb.154.1628781996535; Thu, 12 Aug 2021 08:26:36 -0700 (PDT) MIME-Version: 1.0 References: <09e4b2bd-2055-f0f8-e339-b1aeeff5176a@suse.cz> <18b1cf5b-a80c-fc00-e638-2f5b5d4136a9@suse.cz> In-Reply-To: <18b1cf5b-a80c-fc00-e638-2f5b5d4136a9@suse.cz> From: "H.J. Lu" Date: Thu, 12 Aug 2021 08:26:00 -0700 Message-ID: Subject: Re: [PATCH] i386: support micro-levels in target{, _clone} attrs [PR101696] To: =?UTF-8?Q?Martin_Li=C5=A1ka?= Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3031.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Aug 2021 15:26:39 -0000 On Thu, Aug 12, 2021 at 8:22 AM Martin Li=C5=A1ka wrote: > > On 8/12/21 4:51 PM, H.J. Lu wrote: > > On Thu, Aug 12, 2021 at 7:39 AM Martin Li=C5=A1ka wrot= e: > >> > >> On 8/12/21 4:25 PM, H.J. Lu wrote: > >>> Please send out the v2 patch with the enclosed patch. I added some t= ests. > >> > >> Thanks, there's patch which includes your changes. > >> > >> Martin > > > > diff --git a/gcc/common/config/i386/i386-isas.h > > b/gcc/common/config/i386/i386-isas.h > > index 898c18f3dda..cd9523b8fbc 100644 > > --- a/gcc/common/config/i386/i386-isas.h > > +++ b/gcc/common/config/i386/i386-isas.h > > @@ -169,4 +169,8 @@ ISA_NAMES_TABLE_START > > ISA_NAMES_TABLE_ENTRY("aeskle", FEATURE_AESKLE, P_NONE, NULL) > > ISA_NAMES_TABLE_ENTRY("widekl", FEATURE_WIDEKL, P_NONE, "-mwidekl") > > ISA_NAMES_TABLE_ENTRY("avxvnni", FEATURE_AVXVNNI, P_NONE, "-mavxvnn= i") > > + ISA_NAMES_TABLE_ENTRY("x86-64", FEATURE_X86_64_BASELINE, P_NONE, NUL= L) > > + ISA_NAMES_TABLE_ENTRY("x86-64-v2", FEATURE_X86_64_V2, P_NONE, NULL) > > + ISA_NAMES_TABLE_ENTRY("x86-64-v3", FEATURE_X86_64_V3, P_NONE, NULL) > > + ISA_NAMES_TABLE_ENTRY("x86-64-v4", FEATURE_X86_64_V4, P_NONE, NULL) > > > > If they have proper feature_priority, can you avoid > > I don't think so. First we likely want supporting "arch=3Dx86-64-v3" rath= er than > "x86-64-v3" in e.g. 'target' attribute. That means a special handling by = the code > I added. Will it hurt if they have proper feature_priorities you added? > The following fails as there's no corresponding -m$option. > > pr101696.c:5:45: error: attribute =E2=80=98x86-64-v4=E2=80=99 argument = =E2=80=98target=E2=80=99 is unknown > > 5 | __attribute__ ((target ("x86-64-v4"))) void foo () { __builtin_= printf ("arch=3Dx86-64-v4\n"); } > > | ^~~ > > > Or do I miss something and we can do it in a simpler way? > > Cheers, > Martin > > > > > iff --git a/gcc/config/i386/i386-builtins.c b/gcc/config/i386/i386-buil= tins.c > > index 204e2903126..492873bb076 100644 > > --- a/gcc/config/i386/i386-builtins.c > > +++ b/gcc/config/i386/i386-builtins.c > > @@ -1904,8 +1904,24 @@ get_builtin_code_for_version (tree decl, tree > > *predicate_list) > > return 0; > > new_target =3D TREE_TARGET_OPTION (target_node); > > gcc_assert (new_target); > > - > > - if (new_target->arch_specified && new_target->arch > 0) > > + enum ix86_builtins builtin_fn =3D IX86_BUILTIN_CPU_IS; > > + > > + /* Special case x86-64 micro-level architectures. */ > > + const char *arch_name =3D attrs_str + strlen ("arch=3D"); > > + if (startswith (arch_name, "x86-64")) > > + { > > + arg_str =3D arch_name; > > + builtin_fn =3D IX86_BUILTIN_CPU_SUPPORTS; > > + if (strcmp (arch_name, "x86-64") =3D=3D 0) > > + priority =3D P_X86_64_BASELINE; > > + else if (strcmp (arch_name, "x86-64-v2") =3D=3D 0) > > + priority =3D P_X86_64_V2; > > + else if (strcmp (arch_name, "x86-64-v3") =3D=3D 0) > > + priority =3D P_X86_64_V3; > > + else if (strcmp (arch_name, "x86-64-v4") =3D=3D 0) > > + priority =3D P_X86_64_V4; > > + } > > > > if (predicate_list) > > { > > - predicate_decl =3D ix86_builtins [(int) IX86_BUILTIN_CPU_IS]= ; > > + predicate_decl =3D ix86_builtins [(int) builtin_fn]; > > > > Is this required? > > > --=20 H.J.