* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
@ 2019-02-11 13:11 graham stott via gcc-patches
2019-02-11 13:14 ` H.J. Lu
0 siblings, 1 reply; 13+ messages in thread
From: graham stott via gcc-patches @ 2019-02-11 13:11 UTC (permalink / raw)
To: Uros Bizjak, H.J. Lu; +Cc: GCC Patches
All these patches from HJL have no testcases. Are they even sutable for gcc 9 at this stage
-------- Original message --------
From: Uros Bizjak <ubizjak@gmail.com>
Date: 11/02/2019 12:51 (GMT+00:00)
To: "H.J. Lu" <hjl.tools@gmail.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
On Mon, Feb 11, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Sun, Feb 10, 2019 at 11:25 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> >
> > On Mon, Feb 11, 2019 at 2:04 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> > >
> > > On Sun, Feb 10, 2019 at 1:49 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > > >
> > > > On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > > >
> > > > > > > > + [(const_int 0)]
> > > > > > > > +{
> > > > > > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > > > > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > > > > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > > > > + emit_insn (insn);
> > > > > > > > + DONE;
> > > > > > >
> > > > > > > Please write this simple RTX explicitly in the place of (const_int 0) above.
> > > > > >
> > > > > > rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > >
> > > > > > is easy. How do I write
> > > > > >
> > > > > > rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > >
> > > > > > in place of (const_int 0)?
> > > > >
> > > > > [(set (match_dup 2)
> > > > > (vec_duplicate:V4SI (match_dup 1)))]
> > > > >
> > > > > with
> > > > >
> > > > > "operands[2] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > > > >
> > > > > or even better:
> > > > >
> > > > > "operands[2] = gen_lowpart (V4SImode, operands[0]);"
> > > > >
> > > > > in the preparation statement.
> > > >
> > > > Even shorter is
> > > >
> > > > "operands[0] = gen_lowpart (V4SImode, operands[0]);"
> > > >
> > > > and use (match_dup 0) instead of (match_dup 2) in the RTX.
> > > >
> > > > There is plenty of examples throughout sse.md.
> > > >
> > >
> > > This works:
> > >
> > > (define_insn_and_split "*vec_dupv2si"
> > > [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> > > (vec_duplicate:V2SI
> > > (match_operand:SI 1 "register_operand" "0,0,Yv")))]
> > > "TARGET_MMX || TARGET_MMX_WITH_SSE"
> > > "@
> > > punpckldq\t%0, %0
> > > #
> > > #"
> > > "TARGET_MMX_WITH_SSE && reload_completed"
> > > [(set (match_dup 0)
> > > (vec_duplicate:V4SI (match_dup 1)))]
> > > "operands[0] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > > [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> > > (set_attr "type" "mmxcvt,ssemov,ssemov")
> > > (set_attr "mode" "DI,TI,TI")])
> >
> > If it works, then gen_lowpart is preferred due to extra checks.
> > However, it would result in a paradoxical subreg, so I wonder if these
> > extra checks allow this transformation.
>
> gen_lowpart dosn't work:
Ah, we need lowpart_subreg after reload.
Uros.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-11 13:11 [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE graham stott via gcc-patches
@ 2019-02-11 13:14 ` H.J. Lu
0 siblings, 0 replies; 13+ messages in thread
From: H.J. Lu @ 2019-02-11 13:14 UTC (permalink / raw)
To: graham stott; +Cc: Uros Bizjak, GCC Patches
On Mon, Feb 11, 2019 at 5:11 AM graham stott
<graham.stott@btinternet.com> wrote:
>
> All these patches from HJL have no testcases. Are they even sutable for gcc 9 at this stage
All my changes are covered by
https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00632.html
> -------- Original message --------
> From: Uros Bizjak <ubizjak@gmail.com>
> Date: 11/02/2019 12:51 (GMT+00:00)
> To: "H.J. Lu" <hjl.tools@gmail.com>
> Cc: GCC Patches <gcc-patches@gcc.gnu.org>
> Subject: Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
>
> On Mon, Feb 11, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Sun, Feb 10, 2019 at 11:25 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > >
> > > On Mon, Feb 11, 2019 at 2:04 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> > > >
> > > > On Sun, Feb 10, 2019 at 1:49 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > > > >
> > > > > On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > > > >
> > > > > > > > > + [(const_int 0)]
> > > > > > > > > +{
> > > > > > > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > > > > > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > > > > > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > > > > > + emit_insn (insn);
> > > > > > > > > + DONE;
> > > > > > > >
> > > > > > > > Please write this simple RTX explicitly in the place of (const_int 0) above.
> > > > > > >
> > > > > > > rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > > >
> > > > > > > is easy. How do I write
> > > > > > >
> > > > > > > rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > > >
> > > > > > > in place of (const_int 0)?
> > > > > >
> > > > > > [(set (match_dup 2)
> > > > > > (vec_duplicate:V4SI (match_dup 1)))]
> > > > > >
> > > > > > with
> > > > > >
> > > > > > "operands[2] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > > > > >
> > > > > > or even better:
> > > > > >
> > > > > > "operands[2] = gen_lowpart (V4SImode, operands[0]);"
> > > > > >
> > > > > > in the preparation statement.
> > > > >
> > > > > Even shorter is
> > > > >
> > > > > "operands[0] = gen_lowpart (V4SImode, operands[0]);"
> > > > >
> > > > > and use (match_dup 0) instead of (match_dup 2) in the RTX.
> > > > >
> > > > > There is plenty of examples throughout sse.md.
> > > > >
> > > >
> > > > This works:
> > > >
> > > > (define_insn_and_split "*vec_dupv2si"
> > > > [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> > > > (vec_duplicate:V2SI
> > > > (match_operand:SI 1 "register_operand" "0,0,Yv")))]
> > > > "TARGET_MMX || TARGET_MMX_WITH_SSE"
> > > > "@
> > > > punpckldq\t%0, %0
> > > > #
> > > > #"
> > > > "TARGET_MMX_WITH_SSE && reload_completed"
> > > > [(set (match_dup 0)
> > > > (vec_duplicate:V4SI (match_dup 1)))]
> > > > "operands[0] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > > > [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> > > > (set_attr "type" "mmxcvt,ssemov,ssemov")
> > > > (set_attr "mode" "DI,TI,TI")])
> > >
> > > If it works, then gen_lowpart is preferred due to extra checks.
> > > However, it would result in a paradoxical subreg, so I wonder if these
> > > extra checks allow this transformation.
> >
> > gen_lowpart dosn't work:
>
> Ah, we need lowpart_subreg after reload.
>
> Uros.
--
H.J.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-11 12:51 ` Uros Bizjak
@ 2019-02-11 13:12 ` H.J. Lu
0 siblings, 0 replies; 13+ messages in thread
From: H.J. Lu @ 2019-02-11 13:12 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
In Mon, Feb 11, 2019 at 4:51 AM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On Mon, Feb 11, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Sun, Feb 10, 2019 at 11:25 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > >
> > > On Mon, Feb 11, 2019 at 2:04 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> > > >
> > > > On Sun, Feb 10, 2019 at 1:49 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > > > >
> > > > > On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > > > >
> > > > > > > > > + [(const_int 0)]
> > > > > > > > > +{
> > > > > > > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > > > > > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > > > > > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > > > > > + emit_insn (insn);
> > > > > > > > > + DONE;
> > > > > > > >
> > > > > > > > Please write this simple RTX explicitly in the place of (const_int 0) above.
> > > > > > >
> > > > > > > rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > > >
> > > > > > > is easy. How do I write
> > > > > > >
> > > > > > > rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > > >
> > > > > > > in place of (const_int 0)?
> > > > > >
> > > > > > [(set (match_dup 2)
> > > > > > (vec_duplicate:V4SI (match_dup 1)))]
> > > > > >
> > > > > > with
> > > > > >
> > > > > > "operands[2] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > > > > >
> > > > > > or even better:
> > > > > >
> > > > > > "operands[2] = gen_lowpart (V4SImode, operands[0]);"
> > > > > >
> > > > > > in the preparation statement.
> > > > >
> > > > > Even shorter is
> > > > >
> > > > > "operands[0] = gen_lowpart (V4SImode, operands[0]);"
> > > > >
> > > > > and use (match_dup 0) instead of (match_dup 2) in the RTX.
> > > > >
> > > > > There is plenty of examples throughout sse.md.
> > > > >
> > > >
> > > > This works:
> > > >
> > > > (define_insn_and_split "*vec_dupv2si"
> > > > [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> > > > (vec_duplicate:V2SI
> > > > (match_operand:SI 1 "register_operand" "0,0,Yv")))]
> > > > "TARGET_MMX || TARGET_MMX_WITH_SSE"
> > > > "@
> > > > punpckldq\t%0, %0
> > > > #
> > > > #"
> > > > "TARGET_MMX_WITH_SSE && reload_completed"
> > > > [(set (match_dup 0)
> > > > (vec_duplicate:V4SI (match_dup 1)))]
> > > > "operands[0] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > > > [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> > > > (set_attr "type" "mmxcvt,ssemov,ssemov")
> > > > (set_attr "mode" "DI,TI,TI")])
> > >
> > > If it works, then gen_lowpart is preferred due to extra checks.
> > > However, it would result in a paradoxical subreg, so I wonder if these
> > > extra checks allow this transformation.
> >
> > gen_lowpart dosn't work:
>
> Ah, we need lowpart_subreg after reload.
>
> Uros.
"operands[0] = lowpart_subreg (V4SImode, operands[0],
GET_MODE (operands[0]));"
works.
--
H.J.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-11 12:27 ` H.J. Lu
@ 2019-02-11 12:51 ` Uros Bizjak
2019-02-11 13:12 ` H.J. Lu
0 siblings, 1 reply; 13+ messages in thread
From: Uros Bizjak @ 2019-02-11 12:51 UTC (permalink / raw)
To: H.J. Lu; +Cc: GCC Patches
On Mon, Feb 11, 2019 at 1:26 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Sun, Feb 10, 2019 at 11:25 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> >
> > On Mon, Feb 11, 2019 at 2:04 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> > >
> > > On Sun, Feb 10, 2019 at 1:49 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > > >
> > > > On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > > >
> > > > > > > > + [(const_int 0)]
> > > > > > > > +{
> > > > > > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > > > > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > > > > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > > > > + emit_insn (insn);
> > > > > > > > + DONE;
> > > > > > >
> > > > > > > Please write this simple RTX explicitly in the place of (const_int 0) above.
> > > > > >
> > > > > > rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > >
> > > > > > is easy. How do I write
> > > > > >
> > > > > > rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > >
> > > > > > in place of (const_int 0)?
> > > > >
> > > > > [(set (match_dup 2)
> > > > > (vec_duplicate:V4SI (match_dup 1)))]
> > > > >
> > > > > with
> > > > >
> > > > > "operands[2] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > > > >
> > > > > or even better:
> > > > >
> > > > > "operands[2] = gen_lowpart (V4SImode, operands[0]);"
> > > > >
> > > > > in the preparation statement.
> > > >
> > > > Even shorter is
> > > >
> > > > "operands[0] = gen_lowpart (V4SImode, operands[0]);"
> > > >
> > > > and use (match_dup 0) instead of (match_dup 2) in the RTX.
> > > >
> > > > There is plenty of examples throughout sse.md.
> > > >
> > >
> > > This works:
> > >
> > > (define_insn_and_split "*vec_dupv2si"
> > > [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> > > (vec_duplicate:V2SI
> > > (match_operand:SI 1 "register_operand" "0,0,Yv")))]
> > > "TARGET_MMX || TARGET_MMX_WITH_SSE"
> > > "@
> > > punpckldq\t%0, %0
> > > #
> > > #"
> > > "TARGET_MMX_WITH_SSE && reload_completed"
> > > [(set (match_dup 0)
> > > (vec_duplicate:V4SI (match_dup 1)))]
> > > "operands[0] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > > [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> > > (set_attr "type" "mmxcvt,ssemov,ssemov")
> > > (set_attr "mode" "DI,TI,TI")])
> >
> > If it works, then gen_lowpart is preferred due to extra checks.
> > However, it would result in a paradoxical subreg, so I wonder if these
> > extra checks allow this transformation.
>
> gen_lowpart dosn't work:
Ah, we need lowpart_subreg after reload.
Uros.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-11 7:25 ` Uros Bizjak
@ 2019-02-11 12:27 ` H.J. Lu
2019-02-11 12:51 ` Uros Bizjak
0 siblings, 1 reply; 13+ messages in thread
From: H.J. Lu @ 2019-02-11 12:27 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
On Sun, Feb 10, 2019 at 11:25 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On Mon, Feb 11, 2019 at 2:04 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Sun, Feb 10, 2019 at 1:49 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > >
> > > On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > >
> > > > > > > + [(const_int 0)]
> > > > > > > +{
> > > > > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > > > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > > > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > > > + emit_insn (insn);
> > > > > > > + DONE;
> > > > > >
> > > > > > Please write this simple RTX explicitly in the place of (const_int 0) above.
> > > > >
> > > > > rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > >
> > > > > is easy. How do I write
> > > > >
> > > > > rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > >
> > > > > in place of (const_int 0)?
> > > >
> > > > [(set (match_dup 2)
> > > > (vec_duplicate:V4SI (match_dup 1)))]
> > > >
> > > > with
> > > >
> > > > "operands[2] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > > >
> > > > or even better:
> > > >
> > > > "operands[2] = gen_lowpart (V4SImode, operands[0]);"
> > > >
> > > > in the preparation statement.
> > >
> > > Even shorter is
> > >
> > > "operands[0] = gen_lowpart (V4SImode, operands[0]);"
> > >
> > > and use (match_dup 0) instead of (match_dup 2) in the RTX.
> > >
> > > There is plenty of examples throughout sse.md.
> > >
> >
> > This works:
> >
> > (define_insn_and_split "*vec_dupv2si"
> > [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> > (vec_duplicate:V2SI
> > (match_operand:SI 1 "register_operand" "0,0,Yv")))]
> > "TARGET_MMX || TARGET_MMX_WITH_SSE"
> > "@
> > punpckldq\t%0, %0
> > #
> > #"
> > "TARGET_MMX_WITH_SSE && reload_completed"
> > [(set (match_dup 0)
> > (vec_duplicate:V4SI (match_dup 1)))]
> > "operands[0] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> > (set_attr "type" "mmxcvt,ssemov,ssemov")
> > (set_attr "mode" "DI,TI,TI")])
>
> If it works, then gen_lowpart is preferred due to extra checks.
> However, it would result in a paradoxical subreg, so I wonder if these
> extra checks allow this transformation.
gen_lowpart dosn't work:
#include <mmintrin.h>
__m64
foo (int i)
{
__v2si x = { i, i };
return (__m64) x;
}
(gdb) f 1
#1 0x0000000000ba7cca in gen_reg_rtx (mode=E_V2SImode)
at /export/gnu/import/git/gitlab/x86-gcc/gcc/emit-rtl.c:1155
1155 gcc_assert (can_create_pseudo_p ());
(gdb) bt
#0 fancy_abort (
file=0x22180e0 "/export/gnu/import/git/gitlab/x86-gcc/gcc/emit-rtl.c",
line=1155,
function=0x22193a8 <gen_reg_rtx(machine_mode)::__FUNCTION__> "gen_reg_rtx")
at /export/gnu/import/git/gitlab/x86-gcc/gcc/diagnostic.c:1607
#1 0x0000000000ba7cca in gen_reg_rtx (mode=E_V2SImode)
at /export/gnu/import/git/gitlab/x86-gcc/gcc/emit-rtl.c:1155
#2 0x0000000000bd3044 in copy_to_reg (x=0x7fffea99b528)
at /export/gnu/import/git/gitlab/x86-gcc/gcc/explow.c:594
#3 0x00000000010c7c0a in gen_lowpart_general (mode=E_V4SImode,
x=0x7fffea99b528)
at /export/gnu/import/git/gitlab/x86-gcc/gcc/rtlhooks.c:56
...
#1 0x0000000000ba7cca in gen_reg_rtx (mode=E_V2SImode)
at /export/gnu/import/git/gitlab/x86-gcc/gcc/emit-rtl.c:1155
1155 gcc_assert (can_create_pseudo_p ());
(gdb)
--
H.J.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-11 1:04 ` H.J. Lu
@ 2019-02-11 7:25 ` Uros Bizjak
2019-02-11 12:27 ` H.J. Lu
0 siblings, 1 reply; 13+ messages in thread
From: Uros Bizjak @ 2019-02-11 7:25 UTC (permalink / raw)
To: H.J. Lu; +Cc: GCC Patches
On Mon, Feb 11, 2019 at 2:04 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Sun, Feb 10, 2019 at 1:49 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> >
> > On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> >
> > > > > > + [(const_int 0)]
> > > > > > +{
> > > > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > > + emit_insn (insn);
> > > > > > + DONE;
> > > > >
> > > > > Please write this simple RTX explicitly in the place of (const_int 0) above.
> > > >
> > > > rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > >
> > > > is easy. How do I write
> > > >
> > > > rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > >
> > > > in place of (const_int 0)?
> > >
> > > [(set (match_dup 2)
> > > (vec_duplicate:V4SI (match_dup 1)))]
> > >
> > > with
> > >
> > > "operands[2] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> > >
> > > or even better:
> > >
> > > "operands[2] = gen_lowpart (V4SImode, operands[0]);"
> > >
> > > in the preparation statement.
> >
> > Even shorter is
> >
> > "operands[0] = gen_lowpart (V4SImode, operands[0]);"
> >
> > and use (match_dup 0) instead of (match_dup 2) in the RTX.
> >
> > There is plenty of examples throughout sse.md.
> >
>
> This works:
>
> (define_insn_and_split "*vec_dupv2si"
> [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> (vec_duplicate:V2SI
> (match_operand:SI 1 "register_operand" "0,0,Yv")))]
> "TARGET_MMX || TARGET_MMX_WITH_SSE"
> "@
> punpckldq\t%0, %0
> #
> #"
> "TARGET_MMX_WITH_SSE && reload_completed"
> [(set (match_dup 0)
> (vec_duplicate:V4SI (match_dup 1)))]
> "operands[0] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> (set_attr "type" "mmxcvt,ssemov,ssemov")
> (set_attr "mode" "DI,TI,TI")])
If it works, then gen_lowpart is preferred due to extra checks.
However, it would result in a paradoxical subreg, so I wonder if these
extra checks allow this transformation.
Uros.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-10 21:49 ` Uros Bizjak
@ 2019-02-11 1:04 ` H.J. Lu
2019-02-11 7:25 ` Uros Bizjak
0 siblings, 1 reply; 13+ messages in thread
From: H.J. Lu @ 2019-02-11 1:04 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
On Sun, Feb 10, 2019 at 1:49 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> > > > > + [(const_int 0)]
> > > > > +{
> > > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > > + emit_insn (insn);
> > > > > + DONE;
> > > >
> > > > Please write this simple RTX explicitly in the place of (const_int 0) above.
> > >
> > > rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > >
> > > is easy. How do I write
> > >
> > > rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > >
> > > in place of (const_int 0)?
> >
> > [(set (match_dup 2)
> > (vec_duplicate:V4SI (match_dup 1)))]
> >
> > with
> >
> > "operands[2] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
> >
> > or even better:
> >
> > "operands[2] = gen_lowpart (V4SImode, operands[0]);"
> >
> > in the preparation statement.
>
> Even shorter is
>
> "operands[0] = gen_lowpart (V4SImode, operands[0]);"
>
> and use (match_dup 0) instead of (match_dup 2) in the RTX.
>
> There is plenty of examples throughout sse.md.
>
This works:
(define_insn_and_split "*vec_dupv2si"
[(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
(vec_duplicate:V2SI
(match_operand:SI 1 "register_operand" "0,0,Yv")))]
"TARGET_MMX || TARGET_MMX_WITH_SSE"
"@
punpckldq\t%0, %0
#
#"
"TARGET_MMX_WITH_SSE && reload_completed"
[(set (match_dup 0)
(vec_duplicate:V4SI (match_dup 1)))]
"operands[0] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
[(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
(set_attr "type" "mmxcvt,ssemov,ssemov")
(set_attr "mode" "DI,TI,TI")])
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-10 21:46 ` Uros Bizjak
@ 2019-02-10 21:49 ` Uros Bizjak
2019-02-11 1:04 ` H.J. Lu
0 siblings, 1 reply; 13+ messages in thread
From: Uros Bizjak @ 2019-02-10 21:49 UTC (permalink / raw)
To: H.J. Lu; +Cc: GCC Patches
On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > > > + [(const_int 0)]
> > > > +{
> > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > + emit_insn (insn);
> > > > + DONE;
> > >
> > > Please write this simple RTX explicitly in the place of (const_int 0) above.
> >
> > rtx insn = gen_vec_dupv4si (op0, operands[1]);
> >
> > is easy. How do I write
> >
> > rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> >
> > in place of (const_int 0)?
>
> [(set (match_dup 2)
> (vec_duplicate:V4SI (match_dup 1)))]
>
> with
>
> "operands[2] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
>
> or even better:
>
> "operands[2] = gen_lowpart (V4SImode, operands[0]);"
>
> in the preparation statement.
Even shorter is
"operands[0] = gen_lowpart (V4SImode, operands[0]);"
and use (match_dup 0) instead of (match_dup 2) in the RTX.
There is plenty of examples throughout sse.md.
Uros.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-10 21:01 ` H.J. Lu
@ 2019-02-10 21:46 ` Uros Bizjak
2019-02-10 21:49 ` Uros Bizjak
0 siblings, 1 reply; 13+ messages in thread
From: Uros Bizjak @ 2019-02-10 21:46 UTC (permalink / raw)
To: H.J. Lu; +Cc: GCC Patches
On Sun, Feb 10, 2019 at 10:01 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Sun, Feb 10, 2019 at 2:36 AM Uros Bizjak <ubizjak@gmail.com> wrote:
> >
> > On 2/10/19, H.J. Lu <hjl.tools@gmail.com> wrote:
> > > Emulate MMX vec_dupv2si with SSE. Only SSE register source operand is
> > > allowed.
> > >
> > > PR target/89021
> > > * config/i386/mmx.md (*vec_dupv2si): Changed to
> > > define_insn_and_split and also allow TARGET_MMX_WITH_SSE to
> > > support SSE emulation.
> > > * config/i386/sse.md (*vec_dupv4si): Renamed to ...
> > > (vec_dupv4si): This.
> > > ---
> > > gcc/config/i386/mmx.md | 27 ++++++++++++++++++++-------
> > > gcc/config/i386/sse.md | 2 +-
> > > 2 files changed, 21 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> > > index d360e97c98b..1ee51c5deb7 100644
> > > --- a/gcc/config/i386/mmx.md
> > > +++ b/gcc/config/i386/mmx.md
> > > @@ -1420,14 +1420,27 @@
> > > (set_attr "length_immediate" "1")
> > > (set_attr "mode" "DI")])
> > >
> > > -(define_insn "*vec_dupv2si"
> > > - [(set (match_operand:V2SI 0 "register_operand" "=y")
> > > +(define_insn_and_split "*vec_dupv2si"
> > > + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> > > (vec_duplicate:V2SI
> > > - (match_operand:SI 1 "register_operand" "0")))]
> > > - "TARGET_MMX"
> > > - "punpckldq\t%0, %0"
> > > - [(set_attr "type" "mmxcvt")
> > > - (set_attr "mode" "DI")])
> > > + (match_operand:SI 1 "register_operand" "0,0,Yv")))]
> > > + "TARGET_MMX || TARGET_MMX_WITH_SSE"
> > > + "@
> > > + punpckldq\t%0, %0
> > > + #
> > > + #"
> > > + "&& reload_completed && TARGET_MMX_WITH_SSE"
> >
> > Please fix above.
>
> I will use
>
> "TARGET_MMX_WITH_SSE && reload_completed"
>
> > > + [(const_int 0)]
> > > +{
> > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > + emit_insn (insn);
> > > + DONE;
> >
> > Please write this simple RTX explicitly in the place of (const_int 0) above.
>
> rtx insn = gen_vec_dupv4si (op0, operands[1]);
>
> is easy. How do I write
>
> rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
>
> in place of (const_int 0)?
[(set (match_dup 2)
(vec_duplicate:V4SI (match_dup 1)))]
with
"operands[2] = gen_rtx_REG (V4SImode, REGNO (operands[0]));"
or even better:
"operands[2] = gen_lowpart (V4SImode, operands[0]);"
in the preparation statement.
Uros.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-10 10:36 ` Uros Bizjak
@ 2019-02-10 21:01 ` H.J. Lu
2019-02-10 21:46 ` Uros Bizjak
0 siblings, 1 reply; 13+ messages in thread
From: H.J. Lu @ 2019-02-10 21:01 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
On Sun, Feb 10, 2019 at 2:36 AM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On 2/10/19, H.J. Lu <hjl.tools@gmail.com> wrote:
> > Emulate MMX vec_dupv2si with SSE. Only SSE register source operand is
> > allowed.
> >
> > PR target/89021
> > * config/i386/mmx.md (*vec_dupv2si): Changed to
> > define_insn_and_split and also allow TARGET_MMX_WITH_SSE to
> > support SSE emulation.
> > * config/i386/sse.md (*vec_dupv4si): Renamed to ...
> > (vec_dupv4si): This.
> > ---
> > gcc/config/i386/mmx.md | 27 ++++++++++++++++++++-------
> > gcc/config/i386/sse.md | 2 +-
> > 2 files changed, 21 insertions(+), 8 deletions(-)
> >
> > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> > index d360e97c98b..1ee51c5deb7 100644
> > --- a/gcc/config/i386/mmx.md
> > +++ b/gcc/config/i386/mmx.md
> > @@ -1420,14 +1420,27 @@
> > (set_attr "length_immediate" "1")
> > (set_attr "mode" "DI")])
> >
> > -(define_insn "*vec_dupv2si"
> > - [(set (match_operand:V2SI 0 "register_operand" "=y")
> > +(define_insn_and_split "*vec_dupv2si"
> > + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> > (vec_duplicate:V2SI
> > - (match_operand:SI 1 "register_operand" "0")))]
> > - "TARGET_MMX"
> > - "punpckldq\t%0, %0"
> > - [(set_attr "type" "mmxcvt")
> > - (set_attr "mode" "DI")])
> > + (match_operand:SI 1 "register_operand" "0,0,Yv")))]
> > + "TARGET_MMX || TARGET_MMX_WITH_SSE"
> > + "@
> > + punpckldq\t%0, %0
> > + #
> > + #"
> > + "&& reload_completed && TARGET_MMX_WITH_SSE"
>
> Please fix above.
I will use
"TARGET_MMX_WITH_SSE && reload_completed"
> > + [(const_int 0)]
> > +{
> > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > + emit_insn (insn);
> > + DONE;
>
> Please write this simple RTX explicitly in the place of (const_int 0) above.
rtx insn = gen_vec_dupv4si (op0, operands[1]);
is easy. How do I write
rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
in place of (const_int 0)?
> Uros.
>
> > +}
> > + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> > + (set_attr "type" "mmxcvt,ssemov,ssemov")
> > + (set_attr "mode" "DI,TI,TI")])
> >
> > (define_insn "*mmx_concatv2si"
> > [(set (match_operand:V2SI 0 "register_operand" "=y,y")
> > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> > index 5dc0930ac1f..7d2c0367911 100644
> > --- a/gcc/config/i386/sse.md
> > +++ b/gcc/config/i386/sse.md
> > @@ -18976,7 +18976,7 @@
> > (set_attr "prefix" "maybe_evex,maybe_evex,orig")
> > (set_attr "mode" "V4SF")])
> >
> > -(define_insn "*vec_dupv4si"
> > +(define_insn "vec_dupv4si"
> > [(set (match_operand:V4SI 0 "register_operand" "=v,v,x")
> > (vec_duplicate:V4SI
> > (match_operand:SI 1 "nonimmediate_operand" "Yv,m,0")))]
> > --
> > 2.20.1
> >
> >
--
H.J.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-10 0:20 ` [PATCH 12/43] i386: Emulate MMX vec_dupv2si " H.J. Lu
@ 2019-02-10 10:36 ` Uros Bizjak
2019-02-10 21:01 ` H.J. Lu
0 siblings, 1 reply; 13+ messages in thread
From: Uros Bizjak @ 2019-02-10 10:36 UTC (permalink / raw)
To: H.J. Lu; +Cc: gcc-patches
On 2/10/19, H.J. Lu <hjl.tools@gmail.com> wrote:
> Emulate MMX vec_dupv2si with SSE. Only SSE register source operand is
> allowed.
>
> PR target/89021
> * config/i386/mmx.md (*vec_dupv2si): Changed to
> define_insn_and_split and also allow TARGET_MMX_WITH_SSE to
> support SSE emulation.
> * config/i386/sse.md (*vec_dupv4si): Renamed to ...
> (vec_dupv4si): This.
> ---
> gcc/config/i386/mmx.md | 27 ++++++++++++++++++++-------
> gcc/config/i386/sse.md | 2 +-
> 2 files changed, 21 insertions(+), 8 deletions(-)
>
> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> index d360e97c98b..1ee51c5deb7 100644
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -1420,14 +1420,27 @@
> (set_attr "length_immediate" "1")
> (set_attr "mode" "DI")])
>
> -(define_insn "*vec_dupv2si"
> - [(set (match_operand:V2SI 0 "register_operand" "=y")
> +(define_insn_and_split "*vec_dupv2si"
> + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> (vec_duplicate:V2SI
> - (match_operand:SI 1 "register_operand" "0")))]
> - "TARGET_MMX"
> - "punpckldq\t%0, %0"
> - [(set_attr "type" "mmxcvt")
> - (set_attr "mode" "DI")])
> + (match_operand:SI 1 "register_operand" "0,0,Yv")))]
> + "TARGET_MMX || TARGET_MMX_WITH_SSE"
> + "@
> + punpckldq\t%0, %0
> + #
> + #"
> + "&& reload_completed && TARGET_MMX_WITH_SSE"
Please fix above.
> + [(const_int 0)]
> +{
> + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> + emit_insn (insn);
> + DONE;
Please write this simple RTX explicitly in the place of (const_int 0) above.
Uros.
> +}
> + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> + (set_attr "type" "mmxcvt,ssemov,ssemov")
> + (set_attr "mode" "DI,TI,TI")])
>
> (define_insn "*mmx_concatv2si"
> [(set (match_operand:V2SI 0 "register_operand" "=y,y")
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 5dc0930ac1f..7d2c0367911 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -18976,7 +18976,7 @@
> (set_attr "prefix" "maybe_evex,maybe_evex,orig")
> (set_attr "mode" "V4SF")])
>
> -(define_insn "*vec_dupv4si"
> +(define_insn "vec_dupv4si"
> [(set (match_operand:V4SI 0 "register_operand" "=v,v,x")
> (vec_duplicate:V4SI
> (match_operand:SI 1 "nonimmediate_operand" "Yv,m,0")))]
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-10 0:19 [PATCH 00/43] V3: Emulate MMX intrinsics " H.J. Lu
@ 2019-02-10 0:20 ` H.J. Lu
2019-02-10 10:36 ` Uros Bizjak
0 siblings, 1 reply; 13+ messages in thread
From: H.J. Lu @ 2019-02-10 0:20 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak
Emulate MMX vec_dupv2si with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (*vec_dupv2si): Changed to
define_insn_and_split and also allow TARGET_MMX_WITH_SSE to
support SSE emulation.
* config/i386/sse.md (*vec_dupv4si): Renamed to ...
(vec_dupv4si): This.
---
gcc/config/i386/mmx.md | 27 ++++++++++++++++++++-------
gcc/config/i386/sse.md | 2 +-
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index d360e97c98b..1ee51c5deb7 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1420,14 +1420,27 @@
(set_attr "length_immediate" "1")
(set_attr "mode" "DI")])
-(define_insn "*vec_dupv2si"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
+(define_insn_and_split "*vec_dupv2si"
+ [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
(vec_duplicate:V2SI
- (match_operand:SI 1 "register_operand" "0")))]
- "TARGET_MMX"
- "punpckldq\t%0, %0"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
+ (match_operand:SI 1 "register_operand" "0,0,Yv")))]
+ "TARGET_MMX || TARGET_MMX_WITH_SSE"
+ "@
+ punpckldq\t%0, %0
+ #
+ #"
+ "&& reload_completed && TARGET_MMX_WITH_SSE"
+ [(const_int 0)]
+{
+ /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
+ rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
+ rtx insn = gen_vec_dupv4si (op0, operands[1]);
+ emit_insn (insn);
+ DONE;
+}
+ [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+ (set_attr "type" "mmxcvt,ssemov,ssemov")
+ (set_attr "mode" "DI,TI,TI")])
(define_insn "*mmx_concatv2si"
[(set (match_operand:V2SI 0 "register_operand" "=y,y")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 5dc0930ac1f..7d2c0367911 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -18976,7 +18976,7 @@
(set_attr "prefix" "maybe_evex,maybe_evex,orig")
(set_attr "mode" "V4SF")])
-(define_insn "*vec_dupv4si"
+(define_insn "vec_dupv4si"
[(set (match_operand:V4SI 0 "register_operand" "=v,v,x")
(vec_duplicate:V4SI
(match_operand:SI 1 "nonimmediate_operand" "Yv,m,0")))]
--
2.20.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
2019-02-09 13:24 [PATCH 00/43] V2: Emulate MMX intrinsics " H.J. Lu
@ 2019-02-09 13:24 ` H.J. Lu
0 siblings, 0 replies; 13+ messages in thread
From: H.J. Lu @ 2019-02-09 13:24 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak
Emulate MMX vec_dupv2si with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (*vec_dupv2si): Changed to
define_insn_and_split and also allow TARGET_MMX_WITH_SSE to
support SSE emulation.
* config/i386/sse.md (*vec_dupv4si): Renamed to ...
(vec_dupv4si): This.
---
gcc/config/i386/mmx.md | 27 ++++++++++++++++++++-------
gcc/config/i386/sse.md | 2 +-
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 73fdef3ba1e..e31c3f5c366 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1420,14 +1420,27 @@
(set_attr "length_immediate" "1")
(set_attr "mode" "DI")])
-(define_insn "*vec_dupv2si"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
+(define_insn_and_split "*vec_dupv2si"
+ [(set (match_operand:V2SI 0 "register_operand" "=y,Yx,Yy")
(vec_duplicate:V2SI
- (match_operand:SI 1 "register_operand" "0")))]
- "TARGET_MMX"
- "punpckldq\t%0, %0"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
+ (match_operand:SI 1 "register_operand" "0,0,Yy")))]
+ "TARGET_MMX || TARGET_MMX_WITH_SSE"
+ "@
+ punpckldq\t%0, %0
+ #
+ #"
+ "&& reload_completed && TARGET_MMX_WITH_SSE"
+ [(const_int 0)]
+{
+ /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
+ rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
+ rtx insn = gen_vec_dupv4si (op0, operands[1]);
+ emit_insn (insn);
+ DONE;
+}
+ [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+ (set_attr "type" "mmxcvt,ssemov,ssemov")
+ (set_attr "mode" "DI,TI,TI")])
(define_insn "*mmx_concatv2si"
[(set (match_operand:V2SI 0 "register_operand" "=y,y")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 5dc0930ac1f..7d2c0367911 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -18976,7 +18976,7 @@
(set_attr "prefix" "maybe_evex,maybe_evex,orig")
(set_attr "mode" "V4SF")])
-(define_insn "*vec_dupv4si"
+(define_insn "vec_dupv4si"
[(set (match_operand:V4SI 0 "register_operand" "=v,v,x")
(vec_duplicate:V4SI
(match_operand:SI 1 "nonimmediate_operand" "Yv,m,0")))]
--
2.20.1
^ permalink raw reply [flat|nested] 13+ messages in thread
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2019-02-11 13:11 [PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE graham stott via gcc-patches
2019-02-11 13:14 ` H.J. Lu
-- strict thread matches above, loose matches on Subject: below --
2019-02-10 0:19 [PATCH 00/43] V3: Emulate MMX intrinsics " H.J. Lu
2019-02-10 0:20 ` [PATCH 12/43] i386: Emulate MMX vec_dupv2si " H.J. Lu
2019-02-10 10:36 ` Uros Bizjak
2019-02-10 21:01 ` H.J. Lu
2019-02-10 21:46 ` Uros Bizjak
2019-02-10 21:49 ` Uros Bizjak
2019-02-11 1:04 ` H.J. Lu
2019-02-11 7:25 ` Uros Bizjak
2019-02-11 12:27 ` H.J. Lu
2019-02-11 12:51 ` Uros Bizjak
2019-02-11 13:12 ` H.J. Lu
2019-02-09 13:24 [PATCH 00/43] V2: Emulate MMX intrinsics " H.J. Lu
2019-02-09 13:24 ` [PATCH 12/43] i386: Emulate MMX vec_dupv2si " H.J. Lu
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