From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19900 invoked by alias); 4 Jul 2011 13:43:10 -0000 Received: (qmail 19891 invoked by uid 22791); 4 Jul 2011 13:43:09 -0000 X-SWARE-Spam-Status: No, hits=0.3 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MEDICAL_SUBJECT,RCVD_IN_DNSWL_LOW,TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 04 Jul 2011 13:42:55 +0000 Received: by qwh5 with SMTP id 5so2920613qwh.20 for ; Mon, 04 Jul 2011 06:42:55 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.79.196 with SMTP id q4mr4670221qck.132.1309786974754; Mon, 04 Jul 2011 06:42:54 -0700 (PDT) Received: by 10.229.214.83 with HTTP; Mon, 4 Jul 2011 06:42:54 -0700 (PDT) In-Reply-To: References: <20110630225005.GA1839@intel.com> Date: Mon, 04 Jul 2011 13:43:00 -0000 Message-ID: Subject: Re: PATCH: PR target/49600: Bad SSE2 int->float split in i386.md From: "H.J. Lu" To: Uros Bizjak Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-07/txt/msg00186.txt.bz2 On Mon, Jul 4, 2011 at 3:18 AM, Uros Bizjak wrote: > On Mon, Jul 4, 2011 at 7:13 AM, H.J. Lu wrote: > >>>>> In one SSE2 int->float split, when TARGET_USE_VECTOR_CONVERTS is true, >>>>> TARGET_INTER_UNIT_MOVES is false and GENERAL_REG_P (op1) is true. we >>>>> will get gcc_unreachable. =A0This patch removes TARGET_INTER_UNIT_MOV= ES >>>>> check. =A0OK for trunk? >>>> >>>> This will result in register allocation failure. Operand 0 of >> >> That particular sse2_loadld insn matches: >> >> (insn 49 22 50 5 (set (reg:V4SI 21 xmm0 [83]) >> =A0 =A0 =A0 =A0(vec_merge:V4SI (vec_duplicate:V4SI (reg/v:SI 1 dx [orig:= 64 >> test ] [64])) >> =A0 =A0 =A0 =A0 =A0 =A0(const_vector:V4SI [ >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(const_int 0 [0]) >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(const_int 0 [0]) >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(const_int 0 [0]) >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(const_int 0 [0]) >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0]) >> =A0 =A0 =A0 =A0 =A0 =A0(const_int 1 [0x1]))) x.i:11 1365 {vec_setv4si_0} >> =A0 =A0 (nil)) >> > > Yes, but it should not be generated for !TARGET_INTER_UNIT_MOVES. The > constraint should be Yi, but then we don't shadow other alternatives > correctly. > >>>> sse2_loadld pattern has conditional constraint Yi that depends on >>>> TARGET_INTER_UNIT_MOVES, so we can't blindly generate sse2_loadld >>>> after reload. =A0I'm testing attached patch. >>>> >>>> BTW: Do you perhaps have a testcase for this problem? >>> >>> I have a testcase. But it needs a new x86 optimization we are working o= n it. >>> >>>> 2011-07-03 =A0Uros Bizjak =A0 >>>> >>>> =A0 =A0 =A0 =A0PR target/49600 >>>> =A0 =A0 =A0 =A0* config/i386/i386.md (SSE2 int->float split): Push ope= rand 1 in >>>> =A0 =A0 =A0 =A0general register to memory for !TARGET_INTER_UNIT_MOVES. >>>> >>> >>> I will give it a try. >>> >> >> It doesn't work: I still got > > Yes, I later noticed that I have changed the wrong pattern (the one > with memory clobber) ;( . Attached is the correct patch. > This works. Can you check it in? Thanks. --=20 H.J.