From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14902 invoked by alias); 25 Apr 2012 21:28:51 -0000 Received: (qmail 14892 invoked by uid 22791); 25 Apr 2012 21:28:50 -0000 X-SWARE-Spam-Status: No, hits=-4.9 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,KHOP_RCVD_TRUST,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE X-Spam-Check-By: sourceware.org Received: from mail-qc0-f175.google.com (HELO mail-qc0-f175.google.com) (209.85.216.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 25 Apr 2012 21:28:37 +0000 Received: by qcso7 with SMTP id o7so383616qcs.20 for ; Wed, 25 Apr 2012 14:28:36 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.75.142 with SMTP id y14mr979562qcj.144.1335389316884; Wed, 25 Apr 2012 14:28:36 -0700 (PDT) Received: by 10.229.136.69 with HTTP; Wed, 25 Apr 2012 14:28:36 -0700 (PDT) In-Reply-To: References: <20120330001021.9E30EB2086@azwildcat.mtv.corp.google.com> Date: Wed, 25 Apr 2012 21:28:00 -0000 Message-ID: Subject: Re: Support for Runtime CPU type detection via builtins (issue5754058) From: "H.J. Lu" To: Sriraman Tallam Cc: Uros Bizjak , Richard Guenther , Michael Matz , reply@codereview.appspotmail.com, gcc-patches@gcc.gnu.org, Richard Henderson , Jan Hubicka Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2012-04/txt/msg01641.txt.bz2 On Wed, Apr 25, 2012 at 2:25 PM, Sriraman Tallam wrot= e: > On Tue, Apr 24, 2012 at 7:39 PM, H.J. Lu wrote: >> On Tue, Apr 24, 2012 at 7:06 PM, Sriraman Tallam w= rote: >>> On Tue, Apr 24, 2012 at 5:24 PM, H.J. Lu wrote: >>>> On Tue, Apr 24, 2012 at 5:10 PM, Sriraman Tallam = wrote: >>>>> Hi, >>>>> >>>>> =A0 Thanks for all the comments. I have made all the changes as >>>>> mentioned and submiited the patch. Summary of changes made: >>>>> >>>>> * Add support for AVX >>>>> * Fix documentation in extend.texi >>>>> * Make it thread-safe according to H.J.'s comments. >>>>> >>>>> I have attached the patch. Boot-strapped and checked for test parity >>>>> with pristine build. >>>>> >>>>> =A0 =A0 =A0 * config/i386/i386.c (build_processor_model_struct): New = function. >>>>> =A0 =A0 =A0 =A0(make_var_decl): New function. >>>>> =A0 =A0 =A0 =A0(fold_builtin_cpu): New function. >>>>> =A0 =A0 =A0 =A0(ix86_fold_builtin): New function. >>>>> =A0 =A0 =A0 =A0(make_cpu_type_builtin): New function. >>>>> =A0 =A0 =A0 =A0(ix86_init_platform_type_builtins): New function. >>>>> =A0 =A0 =A0 =A0(ix86_expand_builtin): Expand new builtins by folding = them. >>>>> =A0 =A0 =A0 =A0(ix86_init_builtins): Make new builtins to detect CPU = type. >>>>> =A0 =A0 =A0 =A0(TARGET_FOLD_BUILTIN): New macro. >>>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_INIT): New enum value. >>>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS): New enum value. >>>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_SUPPORTS): New enum value. >>>>> =A0 =A0 =A0 =A0* config/i386/i386-builtin-types.def: New function typ= e. >>>>> =A0 =A0 =A0 =A0* testsuite/gcc.target/builtin_target.c: New testcase. >>>>> =A0 =A0 =A0 =A0* doc/extend.texi: Document builtins. >>>>> >>>>> =A0 =A0 =A0 =A0* libgcc/config/i386/i386-cpuinfo.c: New file. >>>>> =A0 =A0 =A0 =A0* libgcc/config/i386/t-cpuinfo: New file. >>>>> =A0 =A0 =A0 =A0* libgcc/config.host: Include t-cpuinfo. >>>>> =A0 =A0 =A0 =A0* libgcc/config/i386/libgcc-glibc.ver: Version symbol = __cpu_model. >>>>> >>>>> >>>> >>>> + =A0/* This function needs to run just once. =A0*/ >>>> + =A0if (__cpu_model.__cpu_vendor) >>>> + =A0 =A0return 0; >>>> + >>>> + =A0/* Assume cpuid insn present. Run in level 0 to get vendor id. */ >>>> + =A0if (!__get_cpuid_output (0, &eax, &ebx, &ecx, &edx)) >>>> + =A0 =A0return -1; >>>> >>>> If __get_cpuid_output returns non-zero, it will be called >>>> repeatedly. =A0I think you should set __cpu_model.__cpu_vendor >>>> to non-zero in this case. >>> >>> Done now. >>> >>> 2012-04-24 =A0Sriraman Tallam =A0 >>> >>> =A0 =A0 =A0 =A0* libgcc/config/i386/i386-cpuinfo.c: Set __cpu_vendor al= ways. >>> >>> >>> Index: libgcc/config/i386/i386-cpuinfo.c >>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>> --- libgcc/config/i386/i386-cpuinfo.c =A0 (revision 186789) >>> +++ libgcc/config/i386/i386-cpuinfo.c =A0 (working copy) >>> @@ -256,16 +256,25 @@ __cpu_indicator_init (void) >>> >>> =A0 /* Assume cpuid insn present. Run in level 0 to get vendor id. */ >>> =A0 if (!__get_cpuid_output (0, &eax, &ebx, &ecx, &edx)) >>> - =A0 =A0return -1; >>> + =A0 =A0{ >>> + =A0 =A0 =A0__cpu_model.__cpu_vendor =3D VENDOR_OTHER; >>> + =A0 =A0 =A0return -1; >>> + =A0 =A0} >>> >>> =A0 vendor =3D ebx; >>> =A0 max_level =3D eax; >>> >>> =A0 if (max_level < 1) >>> - =A0 =A0return -1; >>> + =A0 =A0{ >>> + =A0 =A0 =A0__cpu_model.__cpu_vendor =3D VENDOR_OTHER; >>> + =A0 =A0 =A0return -1; >>> + =A0 =A0} >>> >>> =A0 if (!__get_cpuid_output (1, &eax, &ebx, &ecx, &edx)) >>> - =A0 =A0return -1; >>> + =A0 =A0{ >>> + =A0 =A0 =A0__cpu_model.__cpu_vendor =3D VENDOR_OTHER; >>> + =A0 =A0 =A0return -1; >>> + =A0 =A0} >>> >>> =A0 model =3D (eax >> 4) & 0x0f; >>> =A0 family =3D (eax >> 8) & 0x0f; >>> >>> >>> Thanks, >> >> Should you also handle AVX2? > > =A0I cannot test it and thought will wait till I get access to a > processor with AVX2. > You can download an AVX2 emulator (SDE) from http://software.intel.com/en-us/avx/ to test AVX2 binaries. --=20 H.J.