From: Dinar Temirbulatov <dtemirbulatov@gmail.com>
To: rdsandiford@googlemail.com
Cc: gcc-patches@gcc.gnu.org
Subject: Re: MIPS Fix PR18141
Date: Fri, 23 Sep 2011 19:58:00 -0000 [thread overview]
Message-ID: <CAMnfPmORP8CYpvCr-Cx6txjjFNixwvNGJpH=cAbHGmXeN44scg@mail.gmail.com> (raw)
In-Reply-To: <CAMnfPmO-CRDanUZxNQCJ10Oy8OQuWmafDH+B67ZBicYmghZ=VQ@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1878 bytes --]
Hi,
I found typo in the patch instead of checking *set_after != 0 it was
set_after != 0, here is corrected version of patch. I retested the
patch without typo on mipsel-unknown-linux-gnu with no new
regressions.
thanks, Dinar.
On Fri, Sep 23, 2011 at 3:11 PM, Dinar Temirbulatov
<dtemirbulatov@gmail.com> wrote:
> hi, Richard,
> This version of patch showed no regressions on mipsel-unknown-linux-gnu.
> Thanks, Dinar.
>
>
> On Wed, Sep 21, 2011 at 4:59 PM, Richard Sandiford
> <rdsandiford@googlemail.com> wrote:
>> Dinar Temirbulatov <dtemirbulatov@gmail.com> writes:
>>> @@ -14696,7 +14696,11 @@ mips_avoid_hazard (rtx after, rtx insn,
>>> clobber hi and lo. */
>>> if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
>>> nops = 2 - *hilo_delay;
>>> - else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
>>> + else if ((*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
>>> + && !((GET_MODE (*delayed_reg) == DFmode && set_after != 0
>>> + && (set = single_set (insn)) != NULL_RTX && GET_MODE (SET_DEST(set)) == DFmode
>>> + && XINT((XEXP (pattern, 1)), 1) == UNSPEC_LOAD_HIGH
>>> + && XINT((XEXP (*set_after, 1)), 1) == UNSPEC_LOAD_LOW)))
>>
>> This isn't safe because the patterns might not be UNSPECs (so XINT (...)
>> would be meaningless). It's better to check the insn code instead.
>> Something like:
>>
>> else if (*delayed_reg != 0
>> && reg_referenced_p (*delayed_reg, pattern)
>> && !(recog_memoized (insn) == CODE_FOR_load_highdf
>> && recog_memoized (*set_after) == CODE_FOR_load_lowdf))
>>
>> (untested). Note that *set_after should always be nonnull if
>> *delayed_reg is.
>>
>> Looks good otherwise.
>>
>> Richard
>>
>
[-- Attachment #2: fix.patch --]
[-- Type: text/x-patch, Size: 3381 bytes --]
diff -ruNp gcc-20110912-orig/gcc/config/mips/mips.c gcc-20110912-fixed/gcc/config/mips/mips.c
--- gcc-20110912-orig/gcc/config/mips/mips.c 2011-09-12 17:22:27.576457121 +0400
+++ gcc-20110912-fixed/gcc/config/mips/mips.c 2011-09-23 18:59:33.329771992 +0400
@@ -14659,20 +14659,20 @@ mips_orphaned_high_part_p (htab_t htab,
INSN and a previous instruction, avoid it by inserting nops after
instruction AFTER.
- *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
- this point. If *DELAYED_REG is non-null, INSN must wait a cycle
- before using the value of that register. *HILO_DELAY counts the
- number of instructions since the last hilo hazard (that is,
- the number of instructions since the last MFLO or MFHI).
+ *DELAYED_REG, *SET_AFTER and *HILO_DELAY describe the hazards that
+ apply at this point. If *DELAYED_REG and *SET_AFTER is non-null,
+ INSN must wait a cycle before using the value of that register.
+ *HILO_DELAY counts the number of instructions since the last hilo hazard
+ (that is, the number of instructions since the last MFLO or MFHI).
- After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
- for the next instruction.
+ After inserting nops for INSN, update *DELAYED_REG, *SET_AFTER
+ and *HILO_DELAY for the next instruction.
LO_REG is an rtx for the LO register, used in dependence checking. */
static void
mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
- rtx *delayed_reg, rtx lo_reg)
+ rtx *delayed_reg, rtx lo_reg, rtx *set_after)
{
rtx pattern, set;
int nops, ninsns;
@@ -14696,7 +14696,9 @@ mips_avoid_hazard (rtx after, rtx insn,
clobber hi and lo. */
if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
nops = 2 - *hilo_delay;
- else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
+ else if ((*delayed_reg != 0 && *set_after != 0 && reg_referenced_p (*delayed_reg, pattern))
+ && !(recog_memoized (insn) == CODE_FOR_load_highdf
+ && recog_memoized (*set_after) == CODE_FOR_load_lowdf))
nops = 1;
else
nops = 0;
@@ -14710,6 +14712,7 @@ mips_avoid_hazard (rtx after, rtx insn,
/* Set up the state for the next instruction. */
*hilo_delay += ninsns;
*delayed_reg = 0;
+ *set_after = 0;
if (INSN_CODE (insn) >= 0)
switch (get_attr_hazard (insn))
{
@@ -14724,6 +14727,7 @@ mips_avoid_hazard (rtx after, rtx insn,
set = single_set (insn);
gcc_assert (set);
*delayed_reg = SET_DEST (set);
+ *set_after = insn;
break;
}
}
@@ -14736,7 +14740,7 @@ mips_avoid_hazard (rtx after, rtx insn,
static void
mips_reorg_process_insns (void)
{
- rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
+ rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg, set_after;
int hilo_delay;
htab_t htab;
@@ -14811,7 +14815,7 @@ mips_reorg_process_insns (void)
INSN_CODE (subinsn) = CODE_FOR_nop;
}
mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
- &delayed_reg, lo_reg);
+ &delayed_reg, lo_reg, &set_after);
}
last_insn = insn;
}
@@ -14832,7 +14836,7 @@ mips_reorg_process_insns (void)
else
{
mips_avoid_hazard (last_insn, insn, &hilo_delay,
- &delayed_reg, lo_reg);
+ &delayed_reg, lo_reg, &set_after);
last_insn = insn;
}
}
[-- Attachment #3: ChangeLog --]
[-- Type: application/octet-stream, Size: 227 bytes --]
PR target/18141
* gcc/config/mips/mips.c (mips_avoid_hazard) Add set_after parameter.
Don't insert nop between CODE_FOR_load_lowdf CODE_FOR_load_highdf.
(mips_reorg_process_insns) Add and handle set_after parameter.
next prev parent reply other threads:[~2011-09-23 17:15 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAMnfPmOfRz+-nPAsWk3iV2=fvF82A157Own02gaJD-YS40Vf4Q@mail.gmail.com>
[not found] ` <g47h5bi5ip.fsf@richards-thinkpad.stglab.manchester.uk.ibm.com>
[not found] ` <CAMnfPmOa=aBBKkvAn3=FxaLfK_kSuNQxBZcDWqHZhnORHmFqDw@mail.gmail.com>
2011-09-21 13:30 ` Richard Sandiford
2011-09-23 13:48 ` Dinar Temirbulatov
2011-09-23 19:58 ` Dinar Temirbulatov [this message]
2011-09-26 9:04 ` Richard Sandiford
2011-09-27 7:48 ` Dinar Temirbulatov
2011-09-27 9:48 ` Richard Sandiford
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