Re: MIPS Fix PR18141

[Dinar Temirbulatov <dtemirbulatov@gmail.com>]

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hi, Richard
On Mon, Sep 26, 2011 at 11:50 AM, Richard Sandiford
<rdsandiford@googlemail.com> wrote:
> Dinar Temirbulatov <dtemirbulatov@gmail.com> writes:
>> I found typo in the patch instead of checking *set_after != 0 it was
>> set_after != 0,  here is corrected version of patch. I retested the
>> patch without typo on mipsel-unknown-linux-gnu with no new
>> regressions.
>
> But my point was that *set_after should always be nonnull if *delayed_reg
> is.  So we shouldn't need that check anyway.
oh, sorry that I missed that.
> The patch looks OK otherwise apart from formatting (the formatting should
> be the same as in the version I suggested before:
>
>  else if (*delayed_reg != 0
>          && reg_referenced_p (*delayed_reg, pattern)
>          && !(recog_memoized (insn) == CODE_FOR_load_highdf
>               && recog_memoized (*set_after) == CODE_FOR_load_lowdf))
>
I prepared the new version of patch, re-tested new version on again on
mipsel-unknown-linux-gnu with no new regressions.
                          thanks, Dinar.

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diff -ruNp gcc-20110912-orig/gcc/config/mips/mips.c gcc-20110912-fixed/gcc/config/mips/mips.c
--- gcc-20110912-orig/gcc/config/mips/mips.c	2011-09-12 17:22:27.576457121 +0400
+++ gcc-20110912-fixed/gcc/config/mips/mips.c	2011-09-27 07:57:28.087366163 +0400
@@ -14659,20 +14659,20 @@ mips_orphaned_high_part_p (htab_t htab,
    INSN and a previous instruction, avoid it by inserting nops after
    instruction AFTER.
 
-   *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
-   this point.  If *DELAYED_REG is non-null, INSN must wait a cycle
-   before using the value of that register.  *HILO_DELAY counts the
-   number of instructions since the last hilo hazard (that is,
-   the number of instructions since the last MFLO or MFHI).
+   *DELAYED_REG, *SET_AFTER and *HILO_DELAY describe the hazards that 
+   apply at this point.  If *DELAYED_REG and *SET_AFTER is non-null, 
+   INSN must wait a cycle before using the value of that register.  
+   *HILO_DELAY counts the number of instructions since the last hilo hazard 
+   (that is, the number of instructions since the last MFLO or MFHI).
 
-   After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
-   for the next instruction.
+   After inserting nops for INSN, update *DELAYED_REG, *SET_AFTER
+   and *HILO_DELAY for the next instruction.
 
    LO_REG is an rtx for the LO register, used in dependence checking.  */
 
 static void
 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
-		   rtx *delayed_reg, rtx lo_reg)
+		   rtx *delayed_reg, rtx lo_reg, rtx *set_after)
 {
   rtx pattern, set;
   int nops, ninsns;
@@ -14696,7 +14696,10 @@ mips_avoid_hazard (rtx after, rtx insn,
      clobber hi and lo.  */
   if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
     nops = 2 - *hilo_delay;
-  else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
+  else if (*delayed_reg != 0 
+	    && reg_referenced_p (*delayed_reg, pattern)
+	    && !(recog_memoized (insn) == CODE_FOR_load_highdf
+	       && recog_memoized (*set_after) == CODE_FOR_load_lowdf))
     nops = 1;
   else
     nops = 0;
@@ -14710,6 +14713,7 @@ mips_avoid_hazard (rtx after, rtx insn,
   /* Set up the state for the next instruction.  */
   *hilo_delay += ninsns;
   *delayed_reg = 0;
+  *set_after = 0;
   if (INSN_CODE (insn) >= 0)
     switch (get_attr_hazard (insn))
       {
@@ -14724,6 +14728,7 @@ mips_avoid_hazard (rtx after, rtx insn,
 	set = single_set (insn);
 	gcc_assert (set);
 	*delayed_reg = SET_DEST (set);
+	*set_after = insn;
 	break;
       }
 }
@@ -14736,7 +14741,7 @@ mips_avoid_hazard (rtx after, rtx insn,
 static void
 mips_reorg_process_insns (void)
 {
-  rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
+  rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg, set_after;
   int hilo_delay;
   htab_t htab;
 
@@ -14811,7 +14816,7 @@ mips_reorg_process_insns (void)
 			INSN_CODE (subinsn) = CODE_FOR_nop;
 		      }
 		    mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
-				       &delayed_reg, lo_reg);
+				       &delayed_reg, lo_reg, &set_after);
 		  }
 	      last_insn = insn;
 	    }
@@ -14832,7 +14837,7 @@ mips_reorg_process_insns (void)
 	      else
 		{
 		  mips_avoid_hazard (last_insn, insn, &hilo_delay,
-				     &delayed_reg, lo_reg);
+				     &delayed_reg, lo_reg, &set_after);
 		  last_insn = insn;
 		}
 	    }

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        PR target/18141
	* gcc/config/mips/mips.c (mips_avoid_hazard) Add set_after parameter.
	Don't insert nop between CODE_FOR_load_lowdf CODE_FOR_load_highdf in 
	case of the same register. (mips_reorg_process_insns) Add and handle 
	set_after parameter.