From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by sourceware.org (Postfix) with ESMTPS id D21AC3858418 for ; Tue, 23 May 2023 20:05:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D21AC3858418 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1ae763f9a94so547585ad.3 for ; Tue, 23 May 2023 13:05:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684872323; x=1687464323; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=qmwFWtXL1JU59BMh8JVqUp1NjiYIAAFGfY0dLAxgs2o=; b=DCvjd7BHgodHJ/bQDnL9h1Y5cRSjBAJ//ibLoSNQISNxCKBzA3jJZwj7toVKUYP2Ev Wuvc0/Cp9Omlg1t9d7J9b0CyGgKy9xRI6Wox/EMfpOayI/A4sZfTMM0HAP4C6QqCCDTJ W3Wh2ET1WpWM0vTnMrevLc2+y3v0CL9cJK2w2AfZXaZRkf2VFq1tugNqh4HmG7q8m/MU g7EuqP2pIzBMRvUVu33vTrhj4bflezZyE3Z0MdNsrN37qEjOPP1d8bY/7EwLp8HEcJ1c kbaRphRNyQc0F7nAdUyjq/gI2JRcsGR/LSSOCnR9DBG2ZFdeqtrjAyc4lXpvefrtf6Jr YgGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684872323; x=1687464323; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qmwFWtXL1JU59BMh8JVqUp1NjiYIAAFGfY0dLAxgs2o=; b=Bj3T5hRfONeqQ2JEUMul+lA2se/RH+x8R2+PZjed9b3c3lOtUE60Vc3pkx33fu7dDV 33K1uhenP8v4yNwmAr3jZ5xErxOvoM2E0EhUZrGwF9W6vgvsshKcs8iAlsWr3zTuIX0T lpdSETzMgBmyrXMKtXMMNU3c/KE2iQMRqKsV5lS4y4gVwjoB/bK2bOd38s5XD+tgOXl5 hwoIB3pvfg4XMOCPTyaClNw7HRzIGdud/S4W3LhXlF9tuCQkytoh03ojF/MCFkHt5ImU bU3xC1Q9hF0Hd1PKEtdt5OVyA44nPIhVzT5MCAl56lqlJ3gjEtXyjOIulTjrQk3sOE1L JUJQ== X-Gm-Message-State: AC+VfDxOhunG0f8b8iIswR4T7QNNig1cRc6dzJt4bcjOBg2v1d8qwl4s Pfpr0v088q49Hhmw5osWDPTdsm6Zjt9TTdwnbuDYPKH85ac= X-Google-Smtp-Source: ACHHUZ4dUpbsnLxpxlfhKyV84hmqUgDFxK7c0s1Nsnytjj3w2EqEpTNjoRZaHrWo3y03xoVm1Dm50bCI0Akex7buKhw= X-Received: by 2002:a17:902:ee41:b0:1ae:626b:4771 with SMTP id 1-20020a170902ee4100b001ae626b4771mr14801427plo.36.1684872323544; Tue, 23 May 2023 13:05:23 -0700 (PDT) MIME-Version: 1.0 References: <5b04c828-7906-2efb-a834-d3ed0ba1f6bd@yahoo.co.jp> In-Reply-To: <5b04c828-7906-2efb-a834-d3ed0ba1f6bd@yahoo.co.jp> From: Max Filippov Date: Tue, 23 May 2023 13:05:12 -0700 Message-ID: Subject: Re: [PATCH v2] xtensa: Optimize '(x & CST1_POW2) != 0 ? CST2_POW2 : 0' To: "Takayuki 'January June' Suwa" Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,FROM_LOCAL_NOVOWEL,HK_RANDOM_ENVFROM,HK_RANDOM_FROM,PLING_QUERY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, May 22, 2023 at 10:48=E2=80=AFPM Takayuki 'January June' Suwa wrote: > > On 2023/05/23 11:27, Max Filippov wrote: > > Hi Suwa-san, > > Hi! > > > This change introduces a bunch of test failures on big endian configura= tion. > > I believe that's because the starting bit position for zero_extract is = counted > > from different ends depending on the endianness. > > Oops, what a stupid mistake... X( > > =3D=3D=3D > This patch decreses one machine instruction from "single bit extraction > with shifting" operation, and tries to eliminate the conditional > branch if CST2_POW2 doesn't fit into signed 12 bits with the help > of ifcvt optimization. > > /* example #1 */ > int test0(int x) { > return (x & 1048576) !=3D 0 ? 1024 : 0; > } > extern int foo(void); > int test1(void) { > return (foo() & 1048576) !=3D 0 ? 16777216 : 0; > } > > ;; before > test0: > movi a9, 0x400 > srai a2, a2, 10 > and a2, a2, a9 > ret.n > test1: > addi sp, sp, -16 > s32i.n a0, sp, 12 > call0 foo > extui a2, a2, 20, 1 > slli a2, a2, 20 > beqz.n a2, .L2 > movi.n a2, 1 > slli a2, a2, 24 > .L2: > l32i.n a0, sp, 12 > addi sp, sp, 16 > ret.n > > ;; after > test0: > extui a2, a2, 20, 1 > slli a2, a2, 10 > ret.n > test1: > addi sp, sp, -16 > s32i.n a0, sp, 12 > call0 foo > l32i.n a0, sp, 12 > extui a2, a2, 20, 1 > slli a2, a2, 24 > addi sp, sp, 16 > ret.n > > In addition, if the left shift amount ('exact_log2(CST2_POW2)') is > between 1 through 3 and a either addition or subtraction with another > register follows, emit a ADDX[248] or SUBX[248] machine instruction > instead of separate left shift and add/subtract ones. > > /* example #2 */ > int test2(int x, int y) { > return ((x & 1048576) !=3D 0 ? 4 : 0) + y; > } > int test3(int x, int y) { > return ((x & 2) !=3D 0 ? 8 : 0) - y; > } > > ;; before > test2: > movi.n a9, 4 > srai a2, a2, 18 > and a2, a2, a9 > add.n a2, a2, a3 > ret.n > test3: > movi.n a9, 8 > slli a2, a2, 2 > and a2, a2, a9 > sub a2, a2, a3 > ret.n > > ;; after > test2: > extui a2, a2, 20, 1 > addx4 a2, a2, a3 > ret.n > test3: > extui a2, a2, 1, 1 > subx8 a2, a2, a3 > ret.n > > gcc/ChangeLog: > > * config/xtensa/predicates.md (addsub_operator): New. > * config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3, > *extzvsi-1bit_addsubx): New insn_and_split patterns. > * config/xtensa/xtensa.cc (xtensa_rtx_costs): > Add a special case about ifcvt 'noce_try_cmove()' to handle > constant loads that do not fit into signed 12 bits in the > patterns added above. > --- > gcc/config/xtensa/predicates.md | 3 ++ > gcc/config/xtensa/xtensa.cc | 3 +- > gcc/config/xtensa/xtensa.md | 83 +++++++++++++++++++++++++++++++++ > 3 files changed, 88 insertions(+), 1 deletion(-) Regtested for target=3Dxtensa-linux-uclibc, no new regressions. Committed to master. --=20 Thanks. -- Max