Re: [PATCH 2/3 v3] xtensa: Add 'adddi3' and 'subdi3' insn patterns

[Max Filippov <jcmvbkbc@gmail.com>]

On Wed, May 31, 2023 at 11:01 PM Takayuki 'January June' Suwa
<jjsuwa_sys3175@yahoo.co.jp> wrote:
> More optimized than the default RTL generation.
>
> gcc/ChangeLog:
>
>         * config/xtensa/xtensa.md (adddi3, subdi3):
>         New RTL generation patterns implemented according to the instruc-
>         tion idioms described in the Xtensa ISA reference manual (p. 600).
> ---
>  gcc/config/xtensa/xtensa.md | 52 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
>
> diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
> index eda1353894b..21afa747e89 100644
> --- a/gcc/config/xtensa/xtensa.md
> +++ b/gcc/config/xtensa/xtensa.md
> @@ -190,6 +190,35 @@
>     (set_attr "mode"    "SI")
>     (set_attr "length"  "3")])
>
> +(define_expand "adddi3"
> +  [(set (match_operand:DI 0 "register_operand")
> +       (plus:DI (match_operand:DI 1 "register_operand")
> +                (match_operand:DI 2 "register_operand")))]
> +  ""
> +{
> +  rtx lo_dest, hi_dest, lo_op0, hi_op0, lo_op1, hi_op1;
> +  rtx_code_label *label;
> +  if (rtx_equal_p (operands[0], operands[1])
> +      || rtx_equal_p (operands[0], operands[2])

> +      || ! REG_P (operands[1]) || ! REG_P (operands[2]))

I wonder if these additional conditions are necessary, given that
the operands have the "register_operand" predicates?

-- 
Thanks.
-- Max