From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by sourceware.org (Postfix) with ESMTPS id D73563858D1E for ; Tue, 23 May 2023 02:28:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D73563858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-51b4ef5378bso6156486a12.1 for ; Mon, 22 May 2023 19:28:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684808885; x=1687400885; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=2XasFGg+71MANQx36bkvETS2vztEIALVUs2i+fanwj0=; b=O3pjdcYm4PHyc4Sx6fQ3wllcIrXQVGoMHiMtCEo/osUnhOfSzdtdzj+3k8lDXm7S3P e+axKFEBYqlxs25HpwPWU9hwG6RdYJZti4YQzMzkr525nQ2qtdxFN3Gze/3xwJEtQZfI rId2eH45huOfoQFd4yOIyD4PILH00BDkLyF2T8gMC5uAtSvRJ5QFNh21rDP7qci9Kd0B ZGeXAoCj1z7SeuD8yzzlO/XSWO4xgqIuAm1IjhlC2CKWqlURIK8k6gmL+MAEkocP5kmg xA+OcHL+ptvQeKGhz1p8sqk8bfGtzsM2x87FeU3MFlIlh+BLvRXkDqOv7bohgBybbg2F B85A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684808885; x=1687400885; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2XasFGg+71MANQx36bkvETS2vztEIALVUs2i+fanwj0=; b=TK2xqjceZMNBSIzQPf3Vs7POq9k25GqcICGkReRn7TCfn+O5YJp0eHAQIxcq0n8kGu 7OFwyOMVQ6cO90mlC2gBgbd4/uDi9I8+zBmQPNjOSvx12O2TGtCQKSr4MCAkGy9uGqj5 eQaKsNtvjSySDk5ew69YQbbC+a8jPSv8JpfcABtVYz+USRuTLJTSEonGjUb9yin+flTJ Q9rS9gG6dvkWIdEXJFs2kMArZuJCY4zu8f5M1qJSNUhFOQ55bOkYBJKP49GOCYqmsA6F LbtHragoaku2EYWwi2LhofJcngt4vuyhwWjfYGKV/sm07mYhLeELL7Tzj+VzhHRtpBsi X2vw== X-Gm-Message-State: AC+VfDwhLvB7C4U+qZWX3YA6pGa6FcE3P5xe7glBctr4qQXCvscSAd3e G1kXFLsGiNfNeZ3VOEJgrAid9J/+Tb62ZY8KhHw= X-Google-Smtp-Source: ACHHUZ59lgJN/sl0M+Wblf45ZjQvU9BT8YB/BaCxgVGanHglqEwrg/hPXJ5+dSOdWpE97/YeGtfyvDBd2CFS2pIWMPM= X-Received: by 2002:a17:903:185:b0:1af:b682:7a78 with SMTP id z5-20020a170903018500b001afb6827a78mr5788549plg.52.1684808884747; Mon, 22 May 2023 19:28:04 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Max Filippov Date: Mon, 22 May 2023 19:27:53 -0700 Message-ID: Subject: Re: [PATCH 1/2] xtensa: Optimize '(x & CST1_POW2) != 0 ? CST2_POW2 : 0' To: "Takayuki 'January June' Suwa" Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,FROM_LOCAL_NOVOWEL,HK_RANDOM_ENVFROM,HK_RANDOM_FROM,PLING_QUERY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Suwa-san, On Mon, May 22, 2023 at 12:06=E2=80=AFAM Takayuki 'January June' Suwa wrote: > > This patch decreses one machine instruction from "single bit extraction > with shifting" operation, and tries to eliminate the conditional > branch if CST2_POW2 doesn't fit into signed 12 bits with the help > of ifcvt optimization. > > /* example #1 */ > int test0(int x) { > return (x & 1048576) !=3D 0 ? 1024 : 0; > } > extern int foo(void); > int test1(void) { > return (foo() & 1048576) !=3D 0 ? 16777216 : 0; > } > > ;; before > test0: > movi a9, 0x400 > srai a2, a2, 10 > and a2, a2, a9 > ret.n > test1: > addi sp, sp, -16 > s32i.n a0, sp, 12 > call0 foo > extui a2, a2, 20, 1 > slli a2, a2, 20 > beqz.n a2, .L2 > movi.n a2, 1 > slli a2, a2, 24 > .L2: > l32i.n a0, sp, 12 > addi sp, sp, 16 > ret.n > > ;; after > test0: > extui a2, a2, 20, 1 > slli a2, a2, 10 > ret.n > test1: > addi sp, sp, -16 > s32i.n a0, sp, 12 > call0 foo > l32i.n a0, sp, 12 > extui a2, a2, 20, 1 > slli a2, a2, 24 > addi sp, sp, 16 > ret.n > > In addition, if the left shift amount ('exact_log2(CST2_POW2)') is > between 1 through 3 and a either addition or subtraction with another > register follows, emit a ADDX[248] or SUBX[248] machine instruction > instead of separate left shift and add/subtract ones. > > /* example #2 */ > int test2(int x, int y) { > return ((x & 1048576) !=3D 0 ? 4 : 0) + y; > } > int test3(int x, int y) { > return ((x & 2) !=3D 0 ? 8 : 0) - y; > } > > ;; before > test2: > movi.n a9, 4 > srai a2, a2, 18 > and a2, a2, a9 > add.n a2, a2, a3 > ret.n > test3: > movi.n a9, 8 > slli a2, a2, 2 > and a2, a2, a9 > sub a2, a2, a3 > ret.n > > ;; after > test2: > extui a2, a2, 20, 1 > addx4 a2, a2, a3 > ret.n > test3: > extui a2, a2, 1, 1 > subx8 a2, a2, a3 > ret.n > > gcc/ChangeLog: > > * config/xtensa/predicates.md (addsub_operator): New. > * config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3, > *extzvsi-1bit_addsubx): New insn_and_split patterns. > * config/xtensa/xtensa.cc (xtensa_rtx_costs): > Add a special case about ifcvt 'noce_try_cmove()' to handle > constant loads that do not fit into signed 12 bits in the > patterns added above. > --- > gcc/config/xtensa/predicates.md | 3 ++ > gcc/config/xtensa/xtensa.cc | 3 +- > gcc/config/xtensa/xtensa.md | 75 +++++++++++++++++++++++++++++++++ > 3 files changed, 80 insertions(+), 1 deletion(-) This change introduces a bunch of test failures on big endian configuration= . I believe that's because the starting bit position for zero_extract is coun= ted from different ends depending on the endianness. --=20 Thanks. -- Max