From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by sourceware.org (Postfix) with ESMTPS id D47ED3858C3A for ; Mon, 20 Nov 2023 14:24:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D47ED3858C3A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D47ED3858C3A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::52d ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700490285; cv=none; b=snVdx8NrHCpaLfuRdgE6veY6myEHD1ZZTIQSs6jgVOd17vudjJgiBh+RbugK5XsrRQ+g6Nh/zUE92rWxueA+n6y4dhDf970Az72JPIG2f8mLHOipEQxnSy53PeiJNU9/wqCkCle/fcJvDOb7DQUx0kRBzccYIBwNg0jliWeTB8g= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700490285; c=relaxed/simple; bh=NtX5E6XDFxry0ZO2T2J1f2VgsZ7Imiwb+ekbApI66IY=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=xv3tdMtPYU7ljC8PZP1JQ7o74IayMigbRG3ByO8eNGdZD5vP3WKN2awCJdsFVM9RFazMdlzn3vM/9JU4FiEtZo9w+jl5MOHZlU8N8a1sUyB6enj7562Y3+/oSIUz8o7NcAAQbSViorWe83/KfxtttPdO6dOg0WcExBuA2YvS4yA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-548ce28fd23so1028935a12.3 for ; Mon, 20 Nov 2023 06:24:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700490281; x=1701095081; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=s/t1rMyeQiSgTl3bZJp2oIEtNVEVd9ZN00YCwrxaB9g=; b=o+KYCmasjY/loAawPXau0hsKCPtCkL0DpbufOsJcA7KWr2Z5InMyUBB5cG1FhrUl4c rVwPlmqPR+ezDKUwNp+eluL2mL2lRzPfgKV6gJMVKUd5MhaUymr0Zw8V1+S/BXnc+NsK WgYT1nzZR3k7HmKtEBBUidaV1bJ1MG9MGAK6dLeJqFVJMjh6lzUadQ6dzlK8wgaHJ/qK JPJ5uX+7u9cS2Q1ZDJVQzMro4dfuZ0XTIaJSwmkAGJDlsFzJ6+0cA86LH3hv56zPLftK SctWsbmQCnAytgTrOZBZ1V5Uo+m66vPZsypZOkhbv1mT35yEdSCNTdTE7ZuheHsyIsAb e94Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700490281; x=1701095081; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=s/t1rMyeQiSgTl3bZJp2oIEtNVEVd9ZN00YCwrxaB9g=; b=PtCcqiSfILgVLNfM7ESXZBcF24iJt71T55IRqfRf2blybe203WftUXbAIfkKZF7xT1 5pM3fl/qvnFSD9sBVFc5LJO2wGzPV7eokLJ1sr6UQXS2WqMy1frf1hGiDhY98urzFJsm JId0kxMtEusmWU2+J21ZvKVzL71KuU1+0UixGaVSp22kHzphEX5y7+Xl3J+m5ZTzKWjq IoCq0v27F+umAee0RSpOZlS8NNEi6HORZ04XXSpvg2NdWkLr2ap1fxkmg3ZsdKArCdvp bcD7vb0yTiySvHdVScZGUR4iNjypPyf6aYO+z3S+0Ho6CHgrkZKbysWzB193iI3G8Qu1 42qg== X-Gm-Message-State: AOJu0Yx16V1lVn3X9OgSilXju891sPZkFWYf6bm0Qk2qq2z9TOMwwJa8 5OtZOUnIM21lSAiqyqUyGZl+S99SVO3PF1SG5mL8mQ== X-Google-Smtp-Source: AGHT+IEV0CYldDGWbeOSxzOUXS6uM1cdP99d8wqjEdpjxsI1QEr+Xyy1t7KJnbITyy9MWt2HPcnNYSkCUBhvRm6nv+o= X-Received: by 2002:a17:906:10b:b0:9e6:59d5:820d with SMTP id 11-20020a170906010b00b009e659d5820dmr5428215eje.2.1700490281527; Mon, 20 Nov 2023 06:24:41 -0800 (PST) MIME-Version: 1.0 References: <20231113142658.69039-1-rearnsha@arm.com> <20231113142658.69039-4-rearnsha@arm.com> <724d822d-7bf1-4284-8688-cc834fd90817@foss.arm.com> In-Reply-To: <724d822d-7bf1-4284-8688-cc834fd90817@foss.arm.com> From: Christophe Lyon Date: Mon, 20 Nov 2023 15:24:39 +0100 Message-ID: Subject: Re: [committed 03/22] arm: testsuite: avoid hard-float ABI incompatibility with -march To: Richard Earnshaw Cc: Richard Earnshaw , "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 20 Nov 2023 at 14:58, Richard Earnshaw wrote: > > > > On 20/11/2023 13:36, Christophe Lyon wrote: > > On Mon, 20 Nov 2023 at 13:44, Richard Earnshaw > > wrote: > >> > >> > >> > >> On 20/11/2023 10:23, Christophe Lyon wrote: > >>> Hi Richard, > >>> > >>> On Mon, 13 Nov 2023 at 15:28, Richard Earnshaw wrote: > >>>> > >>>> > >>>> A number of tests in the gcc testsuite, especially for arm-specific > >>>> targets, add various flags to control the architecture. These run > >>>> into problems when the compiler is configured with -mfpu=auto if the > >>>> new architecture lacks an architectural feature that implies we have > >>>> floating-point instructions. > >>>> > >>>> The testsuite makes this worse as it falls foul of this requirement in > >>>> the base architecture strings provided by target-supports.exp. > >>>> > >>>> To fix this we add "+fp", or something equivalent to this, to all the > >>>> base architecture specifications. The feature will be ignored if the > >>>> float ABI is set to soft. > >>>> > >>>> gcc/testsuite: > >>>> > >>>> * lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok): > >>>> Add base FPU specifications to all architectures that can support > >>>> one. > >>>> --- > >>>> gcc/testsuite/lib/target-supports.exp | 50 +++++++++++++-------------- > >>>> 1 file changed, 25 insertions(+), 25 deletions(-) > >>>> > >>> > >>> Our CI has detected some regressions with this patch, in particular > >>> when testing for cortex-m55: > >>> > >>> with > >>> -mthumb/-march=armv8.1-m.main+mve.fp+fp.dp/-mtune=cortex-m55/-mfloat-abi=hard/-mfpu=auto > >>> and GCC configured with --disable-multilib --with-mode=thumb > >>> --with-arch=armv8.1-m.main+mve.fp+fp.dp --with-float=hard > >>> > >>> you can see our logs here: > >>> https://ci.linaro.org/job/tcwg_gnu_embed_check_gcc--master-thumb_m55_hard_eabi-build/209/artifact/artifacts/00-sumfiles/ > >>> > >>> Thanks, > >>> > >>> Christophe > >> > >> What exactly am I supposed to be looking at here? I see no description > >> of what those logs represent. If they are supposed to be before and > >> after, then why does the after only run a tiny fraction of the testsuite > >> (Running gcc.git~master/gcc/testsuite/gcc.target/arm/arm.exp ... > >> Running gcc.git~master/gcc/testsuite/gcc.target/arm/cmse/cmse.exp ... > >> Running gcc.git~master/gcc/testsuite/gcc.target/arm/lto/lto.exp ...) > >> > >> The logs give no clue as to why the reminder of the testsuite wasn't run. > >> > >> Please don't make me guess. > >> > > > > Here is a summary with the list of regressions: > > https://ci.linaro.org/job/tcwg_gnu_embed_check_gcc--master-thumb_m55_hard_eabi-build/209/artifact/artifacts/notify/regressions.sum/*view*/ > > OK, that's much more useful. But how was I supposed to know that link > existed? > The full notification email contains a lot of information, with several pointers to our Jenkins artifacts. The notification email is not yet automatically sent to contributors because we are still polishing, and I thought I'd save you some time by just sending the useful links. Looks like it's time to send those automatically too. > > > > I thought you'd be able to find your way in the logs above, the .0 > > files contain the logs of the initial full testsuite run, and .1 ones > > contain the logs of the second run of the testsuite, restricted to the > > .exp files where we detected regressions. So looking at gcc.log.1.xz > > will give you details of the regressions shown in the link above. > > There's nothing in the page you sent me to that gives any clue as to how > to read the logs there. So my assumption was that the .0 was a before > run and .1 an after. Please, if you're going to direct people to the > log files, provide some way for them to understand what the log files show. > > Now, to the specific issues: > > Running gcc:gcc.target/arm/arm.exp ... > FAIL: gcc.target/arm/attr_thumb-static2.c (test for excess errors) > UNRESOLVED: gcc.target/arm/attr_thumb-static2.c scan-assembler-times blx 2 > > This was fixed with "arm: testsuite: avoid problems with -mfpu=auto in > attr_thumb-static2.c", which is a later patch in the series (patch 6). > > I don't think it's useful to try to regression test each individual > patch, it wasn't practical to try to get every patch into order in the > series (it would have made for a lot of churn on some files, especially > target-supports.exp), so only a fully before and a fully after run is > useful. If there are issues once the whole series has been applied, > then that is much more interesting. > I looked at this in more detail. That specific bisection build was triggered because we detected regressions, after the full series was committed. What happens is that at the first bad commit (this one) there were more regressions than after the full series was committed. So, the extract of https://ci.linaro.org/job/tcwg_gnu_embed_check_gcc--master-thumb_m55_hard_eabi-build/209/artifact/artifacts/notify/regressions.sum/*view*/ which remains valid on current trunk is: Running gcc:gcc.target/arm/cmse/cmse.exp ... FAIL: gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c -march=armv8-m.main+fp -mthumb -O0 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c -march=armv8-m.main+fp -mthumb -O1 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c -march=armv8-m.main+fp -mthumb -O2 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c -march=armv8-m.main+fp -mthumb -O3 -g scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c -march=armv8-m.main+fp -mthumb -Os scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c -march=armv8-m.main+fp -mthumb -O0 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c -march=armv8-m.main+fp -mthumb -O1 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c -march=armv8-m.main+fp -mthumb -O2 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c -march=armv8-m.main+fp -mthumb -O3 -g scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c -march=armv8-m.main+fp -mthumb -Os scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c -march=armv8-m.main+fp -mthumb -mfloat-abi=soft -O0 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c -march=armv8-m.main+fp -mthumb -mfloat-abi=soft -O1 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c -march=armv8-m.main+fp -mthumb -mfloat-abi=soft -O2 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c -march=armv8-m.main+fp -mthumb -mfloat-abi=soft -O3 -g scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c -march=armv8-m.main+fp -mthumb -mfloat-abi=soft -Os scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c -march=armv8-m.main+fp -mthumb -O0 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c -march=armv8-m.main+fp -mthumb -O1 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c -march=armv8-m.main+fp -mthumb -O2 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c -march=armv8-m.main+fp -mthumb -O3 -g scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c -march=armv8-m.main+fp -mthumb -Os scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c -march=armv8-m.main+fp -mthumb -O0 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c -march=armv8-m.main+fp -mthumb -O1 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c -march=armv8-m.main+fp -mthumb -O2 scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c -march=armv8-m.main+fp -mthumb -O3 -g scan-assembler msr\tAPSR_nzcvqg, lr FAIL: gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c -march=armv8-m.main+fp -mthumb -Os scan-assembler msr\tAPSR_nzcvqg, lr > R.