From: Christophe Lyon <christophe.lyon@linaro.org>
To: Vladimir Makarov <vmakarov.gcc@gmail.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [pushed] [RA]: Modify cost calculation for dealing with pseudo equivalences
Date: Fri, 27 Oct 2023 15:56:44 +0200 [thread overview]
Message-ID: <CAPS5khaRPtYZKf-MP=nP5TmcNHRmvmBHDjCJfLUKxgckkrY=iA@mail.gmail.com> (raw)
In-Reply-To: <a17a915c-db92-7ea3-717a-367a20773e81@gmail.com>
Hi Vladimir,
On Thu, 26 Oct 2023 at 16:00, Vladimir Makarov <vmakarov.gcc@gmail.com> wrote:
>
> This is the second attempt to improve RA cost calculation for pseudos
> with equivalences. The patch explanation is in the log message.
>
> The patch was successfully bootstrapped and tested on x86-64, aarch64,
> and ppc64le. The patch was also benchmarked on x86-64 spec2017.
> specfp2017 performance did not changed, specint2017 improved by 0.3%.
>
As reported by our CI, this patch causes a regression on arm:
FAIL: gcc.target/arm/eliminate.c scan-assembler-times r0,[\\t ]*sp 3
For this testcase, we used to generate:
str lr, [sp, #-4]!
sub sp, sp, #12
add r0, sp, #4
bl bar
add r0, sp, #4
bl bar
add r0, sp, #4
bl bar
add sp, sp, #12
ldr lr, [sp], #4
bx lr
After your patch, we generate:
push {r4, lr}
sub sp, sp, #8
add r4, sp, #4
mov r0, r4
bl bar
mov r0, r4
bl bar
mov r0, r4
bl bar
add sp, sp, #8
pop {r4, lr}
bx lr
which uses 1 more register and 1 more instruction.
Shall I file a bugzilla report for this?
Thanks,
Christophe
next prev parent reply other threads:[~2023-10-27 13:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-26 14:00 Vladimir Makarov
2023-10-27 13:56 ` Christophe Lyon [this message]
2023-10-27 14:18 ` Vladimir Makarov
2023-10-27 14:25 ` Christophe Lyon
2023-11-07 16:18 ` Saurabh Jha
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