* [PATCH] doc: add pdp11 machine constraints
@ 2010-11-04 21:32 Paul Koning
2010-11-05 0:51 ` Joseph S. Myers
0 siblings, 1 reply; 3+ messages in thread
From: Paul Koning @ 2010-11-04 21:32 UTC (permalink / raw)
To: gcc-patches
The machine constraints section was missing the pdp11 target specific constraints. This patch adds them.
Tested with make info, make pdf. Committed.
paul
ChangeLog:
2010-11-04 Paul Koning <ni1d@arrl.net>
* doc/md.texi (Machine Constraints): Add PDP-11 constraints.
Index: doc/md.texi
===================================================================
--- doc/md.texi (revision 166333)
+++ doc/md.texi (working copy)
@@ -2921,6 +2921,55 @@
@end table
+@item PDP-11---@file{config/pdp11/constraints.md}
+@table @code
+@item a
+Floating point registers AC0 through AC3. These can be loaded from/to
+memory with a single instruction.
+
+@item d
+Odd numbered general registers (R1, R3, R5). These are used for 16
+bit multiply operations.
+
+@item f
+Any of the floating point registers (AC0 through AC5).
+
+@item G
+Floating point constant 0.
+
+@item I
+An integer constant that fits in 16 bits.
+
+@item J
+An integer constant whose low order 16 bits are zero.
+
+@item K
+An integer constant that does not meet the constraints for codes
+@samp{I} or @samp{J}.
+
+@item L
+The integer constant 1.
+
+@item M
+The integer constant -1.
+
+@item N
+The integer constant 0.
+
+@item O
+Integer constants -4 through -1 and 1 through 4; shifts by these
+amounts are handled as multiple single-bit shifts rather than a single
+variable-length shift.
+
+@item Q
+A memory reference which requires an additional word (address or
+offset) after the opcode.
+
+@item R
+A memory reference that is encoded within the opcode.
+
+@end table
+
@item RX---@file{config/rx/constraints.md}
@table @code
@item Q
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] doc: add pdp11 machine constraints
2010-11-04 21:32 [PATCH] doc: add pdp11 machine constraints Paul Koning
@ 2010-11-05 0:51 ` Joseph S. Myers
2010-11-05 1:15 ` Paul Koning
0 siblings, 1 reply; 3+ messages in thread
From: Joseph S. Myers @ 2010-11-05 0:51 UTC (permalink / raw)
To: Paul Koning; +Cc: gcc-patches
On Thu, 4 Nov 2010, Paul Koning wrote:
> +Odd numbered general registers (R1, R3, R5). These are used for 16
> +bit multiply operations.
"16-bit", with a hyphen.
> +@item M
> +The integer constant -1.
@minus{}1.
> +Integer constants -4 through -1 and 1 through 4; shifts by these
Likewise, @minus{}4 and @minus{1}.
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] doc: add pdp11 machine constraints
2010-11-05 0:51 ` Joseph S. Myers
@ 2010-11-05 1:15 ` Paul Koning
0 siblings, 0 replies; 3+ messages in thread
From: Paul Koning @ 2010-11-05 1:15 UTC (permalink / raw)
To: Joseph S. Myers; +Cc: gcc-patches
On Nov 4, 2010, at 8:45 PM, Joseph S. Myers wrote:
> On Thu, 4 Nov 2010, Paul Koning wrote:
>
>> +Odd numbered general registers (R1, R3, R5). These are used for 16
>> +bit multiply operations.
>
> "16-bit", with a hyphen.
>
>> +@item M
>> +The integer constant -1.
>
> @minus{}1.
>
>> +Integer constants -4 through -1 and 1 through 4; shifts by these
>
> Likewise, @minus{}4 and @minus{1}.
Thanks! Done.
paul
ChangeLog:
2010-11-04 Paul Koning <ni1d@arrl.net>
* doc/md.texi (Machine Constraints): Correct formatting in PDP-11
constraints.
Index: doc/md.texi
===================================================================
--- doc/md.texi (revision 166335)
+++ doc/md.texi (working copy)
@@ -2928,8 +2928,8 @@
memory with a single instruction.
@item d
-Odd numbered general registers (R1, R3, R5). These are used for 16
-bit multiply operations.
+Odd numbered general registers (R1, R3, R5). These are used for
+16-bit multiply operations.
@item f
Any of the floating point registers (AC0 through AC5).
@@ -2951,13 +2951,13 @@
The integer constant 1.
@item M
-The integer constant -1.
+The integer constant @minus{}1.
@item N
The integer constant 0.
@item O
-Integer constants -4 through -1 and 1 through 4; shifts by these
+Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
amounts are handled as multiple single-bit shifts rather than a single
variable-length shift.
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2010-11-05 0:51 ` Joseph S. Myers
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