From: Lehua Ding <lehua.ding@rivai.ai>
To: Kito Cheng <kito.cheng@gmail.com>
Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai
Subject: Re: [PATCH V5 0/3] RISC-V: Add an experimental vector calling convention
Date: Fri, 8 Sep 2023 14:28:04 +0800 [thread overview]
Message-ID: <CD092E4FD4F39B7B+b5dc65be-9128-4ce2-8c0f-f644480797a7@rivai.ai> (raw)
In-Reply-To: <CA+yXCZCMX2QEbgWhUkCSrVPvE5A8hJJH0LHu=jx76tCqaasT7A@mail.gmail.com>
> Pushed to trunk with few testcase modifications, e.g. adding { target
> { riscv_vector } } to dg-run and adding -march / -mabi for compile
> tests.
Thank you so much Kito for your help :)
--
Best,
Lehua
prev parent reply other threads:[~2023-09-08 6:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-05 7:44 Lehua Ding
2023-09-05 7:44 ` [PATCH V5 1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns Lehua Ding
2023-09-05 7:44 ` [PATCH V5 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed Lehua Ding
2023-09-05 7:44 ` [PATCH V5 3/3] RISC-V: Part-3: Output .variant_cc directive for vector function Lehua Ding
2023-09-05 8:18 ` [PATCH V5 0/3] RISC-V: Add an experimental vector calling convention Kito Cheng
2023-09-06 8:23 ` Kito Cheng
2023-09-08 6:28 ` Lehua Ding [this message]
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