From: "Hurugalawadi, Naveen" <Naveen.Hurugalawadi@cavium.com>
To: James Greenhalgh <james.greenhalgh@arm.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Richard Earnshaw <Richard.Earnshaw@arm.com>,
Marcus Shawcroft <marcus.shawcroft@arm.com>,
"nd@arm.com" <nd@arm.com>,
"Pinski, Andrew" <Andrew.Pinski@cavium.com>
Subject: Re: [PATCH][AArch64] vec_pack_trunc_<mode> should split after register allocator
Date: Tue, 25 Jul 2017 11:40:00 -0000 [thread overview]
Message-ID: <CO2PR07MB269329F7A59287F6C4CDBCBA83B80@CO2PR07MB2693.namprd07.prod.outlook.com> (raw)
In-Reply-To: <20170725085728.GA26092@arm.com>
[-- Attachment #1: Type: text/plain, Size: 433 bytes --]
Hi,
>> I haven't been clear in what I was asking for
Sorry. We understood right with the first comment but the second
part confused us a bit :).
>> Could you switch this back to an insn_and_split as it was in the previous
>> patch, and just drop the && reload_completed ?
Done.
Bootstrapped and Regression done on AArch64-Thunder-Linux.
Please review the patch and let me know if its okay?
Thanks,
Naveen
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[-- Attachment #2: vec_pack-2.patch --]
[-- Type: text/x-diff; name="vec_pack-2.patch", Size: 2410 bytes --]
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 1cb6eeb..0011040 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1291,6 +1291,18 @@
[(set_attr "type" "neon_shift_imm_narrow_q")]
)
+(define_insn "aarch64_simd_vec_pack_trunc_hi_<mode>"
+ [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
+ (vec_concat:<VNARROWQ2>
+ (truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w"))
+ (vec_select:<VNARROWQ>
+ (match_operand:<VNARROWQ2> 3 "register_operand" "0")
+ (match_operand:<VNARROWQ2> 2 "vect_par_cnst_hi_half" ""))))]
+ "TARGET_SIMD"
+ "xtn2\\t%0.<V2ntype>, %1.<Vtype>"
+ [(set_attr "type" "neon_shift_imm_narrow_q")]
+)
+
(define_expand "vec_pack_trunc_<mode>"
[(match_operand:<VNARROWD> 0 "register_operand" "")
(match_operand:VDN 1 "register_operand" "")
@@ -1309,17 +1321,41 @@
;; For quads.
-(define_insn "vec_pack_trunc_<mode>"
+(define_insn_and_split "vec_pack_trunc_<mode>"
[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=&w")
(vec_concat:<VNARROWQ2>
(truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w"))
(truncate:<VNARROWQ> (match_operand:VQN 2 "register_operand" "w"))))]
"TARGET_SIMD"
+ "#"
+ ""
+ [(const_int 0)]
{
if (BYTES_BIG_ENDIAN)
- return "xtn\\t%0.<Vntype>, %2.<Vtype>\;xtn2\\t%0.<V2ntype>, %1.<Vtype>";
+ {
+ rtx low_part = gen_lowpart (<VNARROWQ>mode, operands[0]);
+ emit_insn (gen_aarch64_simd_vec_pack_trunc_<mode> (low_part,
+ operands[2]));
+ rtx high_part = aarch64_simd_vect_par_cnst_half (<VNARROWQ2>mode,
+ true);
+ emit_insn (gen_aarch64_simd_vec_pack_trunc_hi_<mode> (operands[0],
+ operands[1],
+ high_part,
+ operands[0]));
+ }
else
- return "xtn\\t%0.<Vntype>, %1.<Vtype>\;xtn2\\t%0.<V2ntype>, %2.<Vtype>";
+ {
+ rtx low_part = gen_lowpart (<VNARROWQ>mode, operands[0]);
+ emit_insn (gen_aarch64_simd_vec_pack_trunc_<mode> (low_part,
+ operands[1]));
+ rtx high_part = aarch64_simd_vect_par_cnst_half (<VNARROWQ2>mode,
+ true);
+ emit_insn (gen_aarch64_simd_vec_pack_trunc_hi_<mode> (operands[0],
+ operands[2],
+ high_part,
+ operands[0]));
+ }
+ DONE;
}
[(set_attr "type" "multiple")
(set_attr "length" "8")]
next prev parent reply other threads:[~2017-07-25 11:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-27 7:37 Hurugalawadi, Naveen
2017-05-11 5:43 ` [PING] [PATCH] [AArch64] " Hurugalawadi, Naveen
2017-05-26 6:27 ` [PING 2] " Hurugalawadi, Naveen
2017-06-15 3:49 ` [PING 3] " Hurugalawadi, Naveen
2017-06-30 6:29 ` [PING 4] " Hurugalawadi, Naveen
2017-07-19 2:57 ` [PING 5] " Hurugalawadi, Naveen
2017-07-21 16:42 ` [PATCH][AArch64] " James Greenhalgh
2017-07-25 7:30 ` Hurugalawadi, Naveen
2017-07-25 8:57 ` James Greenhalgh
2017-07-25 11:40 ` Hurugalawadi, Naveen [this message]
[not found] ` <CO2PR07MB26932740F6783B49FB886B7983890@CO2PR07MB2693.namprd07.prod.outlook.com>
2017-08-11 6:09 ` [PING] [PATCH] [AArch64] " Hurugalawadi, Naveen
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