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From: "Hurugalawadi, Naveen" <Naveen.Hurugalawadi@cavium.com>
To: Wilco Dijkstra <Wilco.Dijkstra@arm.com>,
	"Pinski, Andrew"	<Andrew.Pinski@cavium.com>
Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>,
	James Greenhalgh	<james.greenhalgh@arm.com>, nd <nd@arm.com>,
	GCC Patches	<gcc-patches@gcc.gnu.org>
Subject: Re: [PING][PATCH][AArch64] Implement ALU_BRANCH fusion
Date: Wed, 26 Apr 2017 12:59:00 -0000	[thread overview]
Message-ID: <CO2PR07MB2694AC291A47AE9109CFC1C283110@CO2PR07MB2694.namprd07.prod.outlook.com> (raw)
In-Reply-To: <VI1PR0802MB26210A218B4677DB9A1EAE01831E0@VI1PR0802MB2621.eurprd08.prod.outlook.com>

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Hi Wilco,

>> Same comment for this part, we want to return true if we match:

Thanks for pointing out about the confusion.

>> Note writing these complex conditions using positive logic makes them much
>> more readable - if you have to negate use !(X && Y && Z) rather than
>> !X || !Y || !Z.

Modified the code as required.

Bootstrapped and Regression tested on AArch64 and X86_64.
Please review the patch and let us know if its okay?

Thanks,
Naveen         

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[-- Attachment #2: alu-branch-5.patch --]
[-- Type: text/x-diff; name="alu-branch-5.patch", Size: 2365 bytes --]

diff --git a/gcc/config/aarch64/aarch64-fusion-pairs.def b/gcc/config/aarch64/aarch64-fusion-pairs.def
index f0e6dbc..300cd00 100644
--- a/gcc/config/aarch64/aarch64-fusion-pairs.def
+++ b/gcc/config/aarch64/aarch64-fusion-pairs.def
@@ -34,5 +34,6 @@ AARCH64_FUSION_PAIR ("movk+movk", MOVK_MOVK)
 AARCH64_FUSION_PAIR ("adrp+ldr", ADRP_LDR)
 AARCH64_FUSION_PAIR ("cmp+branch", CMP_BRANCH)
 AARCH64_FUSION_PAIR ("aes+aesmc", AES_AESMC)
+AARCH64_FUSION_PAIR ("alu+branch", ALU_BRANCH)
 
 #undef AARCH64_FUSION_PAIR
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 2e385c4..1a63ad0 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -792,7 +792,8 @@ static const struct tune_params thunderx2t99_tunings =
   &generic_approx_modes,
   4, /* memmov_cost.  */
   4, /* issue_rate.  */
-  (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC), /* fusible_ops  */
+  (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC
+   | AARCH64_FUSE_ALU_BRANCH), /* fusible_ops  */
   16,	/* function_align.  */
   8,	/* jump_align.  */
   16,	/* loop_align.  */
@@ -13982,6 +13992,49 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
         return true;
     }
 
+  if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH)
+      && any_condjump_p (curr))
+    {
+      /* We're trying to match:
+	  prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
+	  curr (cbz) ==  (set (pc) (if_then_else (eq/ne) (r0)
+							 (const_int 0))
+						 (label_ref ("SYM"))
+						 (pc))  */
+      if (! (SET_DEST (curr_set) == (pc_rtx)
+	     && GET_CODE (SET_SRC (curr_set)) == IF_THEN_ELSE
+	     && REG_P (XEXP (XEXP (SET_SRC (curr_set), 0), 0))
+	     && REG_P (SET_DEST (prev_set))
+	     && REGNO (SET_DEST (prev_set))
+		== REGNO (XEXP (XEXP (SET_SRC (curr_set), 0), 0))))
+	return true;
+
+      /* Fuse ALU operations followed by conditional branch instruction.  */
+      switch (get_attr_type (prev))
+	{
+	case TYPE_ALU_IMM:
+	case TYPE_ALU_SREG:
+	case TYPE_ADC_REG:
+	case TYPE_ADC_IMM:
+	case TYPE_ADCS_REG:
+	case TYPE_ADCS_IMM:
+	case TYPE_LOGIC_REG:
+	case TYPE_LOGIC_IMM:
+	case TYPE_CSEL:
+	case TYPE_ADR:
+	case TYPE_MOV_IMM:
+	case TYPE_SHIFT_REG:
+	case TYPE_SHIFT_IMM:
+	case TYPE_BFM:
+	case TYPE_RBIT:
+	case TYPE_REV:
+	case TYPE_EXTEND:
+	  return true;
+
+	default:;
+	}
+    }
+
   return false;
 }
 


  reply	other threads:[~2017-04-26 12:52 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <VI1PR0802MB26218E2C0940948518A0571783210@VI1PR0802MB2621.eurprd08.prod.outlook.com>
2017-03-15 15:20 ` [PATCH][AArch64] " Wilco Dijkstra
2017-03-21  5:37   ` Andrew Pinski
2017-03-27  7:33     ` Hurugalawadi, Naveen
2017-04-25  7:44       ` [PING][PATCH][AArch64] " Hurugalawadi, Naveen
2017-04-25 11:39         ` Wilco Dijkstra
2017-04-26 12:59           ` Hurugalawadi, Naveen [this message]
2017-04-26 14:29             ` Wilco Dijkstra
2017-04-27  7:32               ` Hurugalawadi, Naveen
2017-05-11  4:57                 ` [PING] [PATCH] [AArch64] " Hurugalawadi, Naveen
2017-05-26  7:14                   ` [PING 2] " Hurugalawadi, Naveen
2017-05-26 11:39                     ` Wilco Dijkstra
2017-06-14 10:29                       ` [PING 3] " Hurugalawadi, Naveen
2017-06-14 11:37                 ` [PING][PATCH][AArch64] " James Greenhalgh

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