From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id 54A273858D20 for ; Thu, 31 Aug 2023 10:47:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 54A273858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp65t1693478835tz61byvi Received: from [10.101.11.9] ( [113.104.210.73]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 31 Aug 2023 18:47:14 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: IcCSTr/hHjOnb6/TA2l8fn/Zt6NKSBHQOtdltCXXhYxDTCarr2UWLt7eFBB+K nqett4aI3lqbb44+kMf9wTYlj2RotCwvCE+S6Z/aNWhLJdNDx0o7tznGjG9do8HYgTAKVK4 jLptmNWisk/8l779Yj1+XiO2TsYv1fA4udIPnZOsLItxx09065BnGJrF1/z2U6ssK3xfCTi WLZS0kiWr+K54zky4dCwE7Uze2JKuckx/QNXBgzI1lLeyU8nafkqgU/kDmAL07jyb90JBmS K15pGwZm0VdNsX7mfKQxJzcjZ8l6q8TaKThRCwrxr5NsWokYXvD3XekW0QF/pZr2esEoRK5 VFr1nSv4wFMsSqVGXsNsdj8E70QlJ64xU+B2ptOovk10IPczh3yj822M7+5zHi2t3dahcS2 mmkVTAzx+QU= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 16389323225953825719 Message-ID: Date: Thu, 31 Aug 2023 18:47:14 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] RISC-V: Change vsetvl tail and mask policy to default policy Content-Language: en-US To: Kito Cheng Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai References: <20230831090621.2687116-1-lehua.ding@rivai.ai> From: Lehua Ding In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,FORGED_MUA_MOZILLA,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_PASS,TXREP,T_SPF_HELO_TEMPERROR,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed, thanks Kito. On 2023/8/31 17:13, Kito Cheng via Gcc-patches wrote: > LGTM > > On Thu, Aug 31, 2023 at 5:07 PM Lehua Ding wrote: >> >> This patch change the vsetvl policy to default policy >> (returned by get_prefer_mask_policy and get_prefer_tail_policy) instead >> fixed policy. Any policy is now returned, allowing change to agnostic >> or undisturbed. In the future, users may be able to control the default >> policy, such as keeping agnostic by compiler options. >> >> gcc/ChangeLog: >> >> * config/riscv/riscv-protos.h (IS_AGNOSTIC): Move to here. >> * config/riscv/riscv-v.cc (gen_no_side_effects_vsetvl_rtx): >> Change to default policy. >> * config/riscv/riscv-vector-builtins-bases.cc: Change to default policy. >> * config/riscv/riscv-vsetvl.h (IS_AGNOSTIC): Delete. >> * config/riscv/riscv.cc (riscv_print_operand): Use IS_AGNOSTIC to test. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/rvv/base/binop_vx_constraint-171.c: Adjust. >> * gcc.target/riscv/rvv/base/binop_vx_constraint-173.c: Adjust. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: New test. >> >> --- >> gcc/config/riscv/riscv-protos.h | 3 +++ >> gcc/config/riscv/riscv-v.cc | 4 +++- >> gcc/config/riscv/riscv-vector-builtins-bases.cc | 8 ++++---- >> gcc/config/riscv/riscv-vsetvl.h | 2 -- >> gcc/config/riscv/riscv.cc | 3 +-- >> .../riscv/rvv/base/binop_vx_constraint-171.c | 4 ++-- >> .../riscv/rvv/base/binop_vx_constraint-173.c | 4 ++-- >> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c | 11 +++++++++++ >> 8 files changed, 26 insertions(+), 13 deletions(-) >> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c >> >> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h >> index 92e30a10f3c..e145ee6c69b 100644 >> --- a/gcc/config/riscv/riscv-protos.h >> +++ b/gcc/config/riscv/riscv-protos.h >> @@ -406,6 +406,9 @@ enum mask_policy >> MASK_ANY = 2, >> }; >> >> +/* Return true if VALUE is agnostic or any policy. */ >> +#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1)) >> + >> enum class reduction_type >> { >> UNORDERED, >> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc >> index 427700192a3..6228ff3d92e 100644 >> --- a/gcc/config/riscv/riscv-v.cc >> +++ b/gcc/config/riscv/riscv-v.cc >> @@ -1672,9 +1672,11 @@ static rtx >> gen_no_side_effects_vsetvl_rtx (machine_mode vmode, rtx vl, rtx avl) >> { >> unsigned int sew = get_sew (vmode); >> + rtx tail_policy = gen_int_mode (get_prefer_tail_policy (), Pmode); >> + rtx mask_policy = gen_int_mode (get_prefer_mask_policy (), Pmode); >> return gen_vsetvl_no_side_effects (Pmode, vl, avl, gen_int_mode (sew, Pmode), >> gen_int_mode (get_vlmul (vmode), Pmode), >> - const0_rtx, const0_rtx); >> + tail_policy, mask_policy); >> } >> >> /* GET VL * 2 rtx. */ >> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc >> index 54582ee130c..8e679f72392 100644 >> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc >> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc >> @@ -139,11 +139,11 @@ public: >> /* LMUL. */ >> e.add_input_operand (Pmode, gen_int_mode (get_vlmul (mode), Pmode)); >> >> - /* TA. */ >> - e.add_input_operand (Pmode, gen_int_mode (1, Pmode)); >> + /* TAIL_ANY. */ >> + e.add_input_operand (Pmode, gen_int_mode (get_prefer_tail_policy (), Pmode)); >> >> - /* MU. */ >> - e.add_input_operand (Pmode, gen_int_mode (0, Pmode)); >> + /* MASK_ANY. */ >> + e.add_input_operand (Pmode, gen_int_mode (get_prefer_mask_policy (), Pmode)); >> return e.generate_insn (code_for_vsetvl_no_side_effects (Pmode)); >> } >> }; >> diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h >> index 2a315e45f31..53549abfac5 100644 >> --- a/gcc/config/riscv/riscv-vsetvl.h >> +++ b/gcc/config/riscv/riscv-vsetvl.h >> @@ -21,8 +21,6 @@ along with GCC; see the file COPYING3. If not see >> #ifndef GCC_RISCV_VSETVL_H >> #define GCC_RISCV_VSETVL_H >> >> -#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1)) >> - >> namespace riscv_vector { >> >> /* Classification of vsetvl instruction. */ >> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc >> index d84fa2311fa..8bca8075713 100644 >> --- a/gcc/config/riscv/riscv.cc >> +++ b/gcc/config/riscv/riscv.cc >> @@ -5246,8 +5246,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) >> else if (code == CONST_INT) >> { >> /* Tail && Mask policy. */ >> - bool agnostic_p = UINTVAL (op) & 0x1; >> - asm_fprintf (file, "%s", agnostic_p ? "a" : "u"); >> + asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "u"); >> } >> else >> output_operand_lossage ("invalid vector constant"); >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c >> index dae5eff42ce..6e8669ae59e 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c >> @@ -7,7 +7,7 @@ >> /* >> ** f1: >> ** ... >> -** vsetivli\t[a-x0-9]+,\s*4,e64,m1,tu,m[au] >> +** vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au] >> ** ... >> ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] >> ** ... >> @@ -41,7 +41,7 @@ void f1 (void * in, void *out, int64_t x, int n) >> /* >> ** f2: >> ** ... >> -** vsetivli\t[a-x0-9]+,\s*4,e64,m1,tu,m[au] >> +** vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au] >> ** ... >> ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] >> ** ... >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c >> index 0d5a2603856..af9c45e942b 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c >> @@ -7,7 +7,7 @@ >> /* >> ** f1: >> ** ... >> -** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,tu,m[au] >> +** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au] >> ** ... >> ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] >> ** ... >> @@ -41,7 +41,7 @@ void f1 (void * in, void *out, int64_t x, int vl) >> /* >> ** f2: >> ** ... >> -** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,tu,m[au] >> +** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au] >> ** ... >> ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] >> ** ... >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c >> new file mode 100644 >> index 00000000000..1703c739f5e >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c >> @@ -0,0 +1,11 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ >> + >> +#include >> + >> +size_t foo () >> +{ >> + return __riscv_vsetvlmax_e8m1 (); >> +} >> + >> +/* { dg-final { scan-assembler-times {\tvsetvli\t[a-x0-9]+,zero,e8,m1,ta,ma} 1 } } */ >> -- >> 2.36.3 >> -- Best, Lehua