Hi, Richi. 
Thanks for taking care of this issue.

From my observation,  VNx2BI is using 2-bit mask: 00 = 0, 01 = 1
                                     VNx4BI is using 4-bit mask: 0000 = 0, 0001 = 1
This perfectly works for ARM SVE since this is the layout of ARM mask register.
However, RVV is always using compact mask that is using 1-bit mask.
That's why it doesn't work for RVV.

For X86, I think it wouldn't be the issue since X86 is always constant mask:
VECTOR_BOOL_MODE (NAME, COUNT, COMPONENT, BYTESIZE)

X86 can always adjust the compact bit by this define.
Wheras, RVV is scalable vector which always uses ADJUST_NUNTIS and ADJUST_BYTESIZE && ADJUST_PRECISION.
So this will make a confusion to GCC.

Thanks.


juzhe.zhong@rivai.ai
 
From: Richard Biener
Date: 2023-06-28 15:17
To: Jeff Law
CC: Kito Cheng; juzhe.zhong@rivai.ai; gcc-patches; kito.cheng; palmer; palmer; Robin Dapp
Subject: Re: [PATCH V2] RISC-V: Fix bug of pre-calculated const vector mask
On Wed, Jun 28, 2023 at 6:09 AM Jeff Law via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
>
>
> On 6/27/23 21:16, Kito Cheng wrote:
> > Do you mind giving some comments about what the difference between the
> > two versions?
> And I'd like a before/after assembly code with the example in the commit
> message.  I didn't see the same behavior when I tried it earlier today
> and ran out of time to dig into it further.
>
> Juzhe -- most folks wait ~1wk to ping patches, even codegen bugfixes.
> Pinging this fast runs the risk of irritating others.  Please be patient.
 
I think if we get constant mask expansion wrong this has to be fixed in
generic code.  ISTR fixing similar issues with AVX512 compact masks.
 
But maybe I'm misunderstanding the problem and the issue only
exists in the backend?
 
Richard.
 
> Jeff