Re: [PATCH] Add zero-overhead looping for xtensa backend

["Yangfei (Felix)" <felix.yang@huawei.com>]

> 
> On Thu, Oct 23, 2014 at 9:12 PM, Yangfei (Felix) <felix.yang@huawei.com> wrote:
> >> Here the key point is we need a general purpose register for the "loop"
> >> instruction.
> 
> So the question to ask here is, "How does this work today, without loop
> instructions?" Somehow--even when it has been spilled--a branch instruction can
> test the trip count. There should be no difference.
> 
> >> And we cannot use zero-cost looping in this situation.
> >> And that's why I spilt the zero_cost_loop_end into a normal test and branch.
> 
> > Also note that the hwloop_pattern_reg interface also expects a general
> purpose register in the doloop_end pattern.
> 
> If there were no loop instruction, how would this work?


Just take a look at my patch. I handle this in the new define_split:

+(define_split
+  [(set (pc)
+        (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "")
+                          (const_int 1))
+                      (label_ref (match_operand 1 "" ""))
+                      (pc)))
+   (set (match_operand:SI 2 "nonimmediate_operand" "")
+        (plus:SI (match_dup 0)
+                 (const_int -1)))
+   (unspec [(const_int 0)] UNSPEC_LSETUP_END)
+   (clobber (match_scratch 3))]
+  "TARGET_LOOPS && optimize && reload_completed"
+  [(const_int 0)]
+{
+  if (!REG_P (operands[0]))
+    {
+      rtx test;
+
+      /* Fallback into a normal conditional branch insn.  */
+      emit_move_insn (operands[3], operands[0]);
+      emit_insn (gen_addsi3 (operands[3], operands[3], constm1_rtx));
+      emit_move_insn (operands[0], operands[3]);
+      test = gen_rtx_NE (VOIDmode, operands[3], const0_rtx);
+      emit_jump_insn (gen_cbranchsi4 (test, operands[3],
+                                      const0_rtx, operands[1]));
+    }
+  else
+    {
+      emit_jump_insn (gen_loop_end (operands[0], operands[1], operands[2]));
+    }
+
+  DONE;
+})