* [PATCH 3/5][AArch64] Crypto SM4 Support
@ 2018-01-03 17:26 Michael Collison
2018-01-09 17:57 ` James Greenhalgh
0 siblings, 1 reply; 2+ messages in thread
From: Michael Collison @ 2018-01-03 17:26 UTC (permalink / raw)
To: GCC Patches; +Cc: nd
[-- Attachment #1: Type: text/plain, Size: 2465 bytes --]
Hi All,
This patch adds support for the SM3/SM4 cryptographic instructions added in Armv8.4-a. Support for the new instructions is in the form of new ACLE intrinsics. A new command line feature modifier, +sm4, is added to enable the support.
Test cases were added to verify that the ACLE Intrinsics generate the appropriate SM3/SM4 assembly instructions.
Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all instructions assembly correctly.
Okay for trunk?
2017-11-10 Michael Collison <michael.collison@arm.com>
* config/aarch64/aarch64-builtins.c:
(aarch64_types_quadopu_imm_qualifiers, TYPES_QUADOPUI): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins):
(__ARM_FEATURE_SM3): Define if TARGET_SM4 is true.
(__ARM_FEATURE_SM4): Define if TARGET_SM4 is true.
* config/aarch64/aarch64.h (AARCH64_FL_SM4): New flags.
(AARCH64_ISA_SM4): New ISA flag.
(TARGET_SM4): New feature flag for sm4.
* config/aarch64/aarch64-simd-builtins.def
(aarch64_sm3ss1qv4si): Ditto.
(aarch64_sm3tt1aq4si): Ditto.
(aarch64_sm3tt1bq4si): Ditto.
(aarch64_sm3tt2aq4si): Ditto.
(aarch64_sm3tt2bq4si): Ditto.
(aarch64_sm3partw1qv4si): Ditto.
(aarch64_sm3partw2qv4si): Ditto.
(aarch64_sm4eqv4si): Ditto.
(aarch64_sm4ekeyqv4si): Ditto.
* config/aarch64/aarch64-simd.md:
(aarch64_sm3ss1qv4si): Ditto.
(aarch64_sm3tt<sm3tt_op>qv4si): Ditto.
(aarch64_sm3partw<sm3part_op>qv4si): Ditto.
(aarch64_sm4eqv4si): Ditto.
(aarch64_sm4ekeyqv4si): Ditto.
* config/aarch64/iterators.md (sm3tt_op): New int iterator.
(sm3part_op): Ditto.
(CRYPTO_SM3TT): Ditto.
(CRYPTO_SM3PART): Ditto.
(UNSPEC_SM3SS1): New unspec.
(UNSPEC_SM3TT1A): Ditto.
(UNSPEC_SM3TT1B): Ditto.
(UNSPEC_SM3TT2A): Ditto.
(UNSPEC_SM3TT2B): Ditto.
(UNSPEC_SM3PARTW1): Ditto.
(UNSPEC_SM3PARTW2): Ditto.
(UNSPEC_SM4E): Ditto.
(UNSPEC_SM4EKEY): Ditto.
* config/aarch64/constraints.md (Ui2): New constraint.
* config/aarch64/predicates.md (aarch64_imm2): New predicate.
* config/arm/types.md (crypto_sm3): New type attribute.
(crypto_sm4): Ditto.
* config/aarch64/arm_neon.h (vsm3ss1q_u32): New intrinsic.
(vsm3tt1aq_u32): Ditto.
(vsm3tt1bq_u32): Ditto.
(vsm3tt2aq_u32): Ditto.
(vsm3tt2bq_u32): Ditto.
(vsm3partw1q_u32): Ditto.
(vsm3partw2q_u32): Ditto.
(vsm4eq_u32): Ditto.
(vsm4ekeyq_u32): Ditto.
(doc/invoke.texi): Document new sm4 option.
gcc.target/aarch64/sm3_sm4.c: New testcase.
[-- Attachment #2: crypto_sm4.patch --]
[-- Type: application/octet-stream, Size: 18235 bytes --]
diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 8cbdb0112032a8c1485c4b466bb6010e89fd013d..4d7b5d7b87948b6d997c73a44ab2d294ef494b28 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -175,6 +175,12 @@ aarch64_types_quadopu_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define TYPES_QUADOPU_LANE (aarch64_types_quadopu_lane_qualifiers)
static enum aarch64_type_qualifiers
+aarch64_types_quadopu_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
+ qualifier_unsigned, qualifier_immediate };
+#define TYPES_QUADOPUI (aarch64_types_quadopu_imm_qualifiers)
+
+static enum aarch64_type_qualifiers
aarch64_types_binop_imm_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_poly, qualifier_none, qualifier_immediate };
#define TYPES_GETREGP (aarch64_types_binop_imm_p_qualifiers)
diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index 95fd021b8a1b445b1bf10615def98c965ea9ebfe..f02dea58361037ca79a63c481e93fc483922abb6 100644
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -137,6 +137,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
aarch64_def_or_undef (TARGET_AES, "__ARM_FEATURE_AES", pfile);
aarch64_def_or_undef (TARGET_SHA2, "__ARM_FEATURE_SHA2", pfile);
+ aarch64_def_or_undef (TARGET_SM4, "__ARM_FEATURE_SM3", pfile);
+ aarch64_def_or_undef (TARGET_SM4, "__ARM_FEATURE_SM4", pfile);
/* Not for ACLE, but required to keep "float.h" correct if we switch
target between implementations that do or do not support ARMv8.2-A
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index df67fdced7a4fa5e485fcb47462778afb2c9039b..e42c4dff774adbb05a67d61cd23b52db3fa8ce96 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -39,19 +39,19 @@
that are required. Their order is not important. */
/* Enabling "fp" just enables "fp".
- Disabling "fp" also disables "simd", "crypto", "fp16", "aes" and "sha2". */
+ Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2" and sm3/sm4. */
AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO |\
- AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, "fp")
+ AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SM4, "fp")
/* Enabling "simd" also enables "fp".
- Disabling "simd" also disables "crypto", "dotprod", "aes" and "sha2". */
+ Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2" and "sm3/sm4". */
AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, AARCH64_FL_CRYPTO |\
- AARCH64_FL_DOTPROD | AARCH64_FL_AES | AARCH64_FL_SHA2, "asimd")
+ AARCH64_FL_DOTPROD | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SM4, "asimd")
-/* Enabling "crypto" also enables "fp", "simd", "aes", and "sha2".
- Disabling "crypto" disables "crypto", "aes", and "sha2". */
+/* Enabling "crypto" also enables "fp" and "simd".
+ Disabling "crypto" disables "crypto", "aes", "sha2" and "sm3/sm4". */
AARCH64_OPT_EXTENSION("crypto", AARCH64_FL_CRYPTO, AARCH64_FL_FP | AARCH64_FL_SIMD,\
- AARCH64_FL_AES | AARCH64_FL_SHA2, "aes pmull sha1 sha2")
+ AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SM4, "aes pmull sha1 sha2")
/* Enabling or disabling "crc" only changes "crc". */
AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, "crc32")
@@ -82,4 +82,8 @@ AARCH64_OPT_EXTENSION("aes", AARCH64_FL_AES, AARCH64_FL_SIMD, 0, "aes")
Disabling "sha2" just disables "sha2". */
AARCH64_OPT_EXTENSION("sha2", AARCH64_FL_SHA2, AARCH64_FL_SIMD, 0, "sha1 sha2")
+/* Enabling "sm4" also enables "simd".
+ Disabling "sm4" just disables "sm4". */
+AARCH64_OPT_EXTENSION("sm4", AARCH64_FL_SM4, AARCH64_FL_SIMD, 0, "sm3 sm4")
+
#undef AARCH64_OPT_EXTENSION
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 52d01342372e518b1238ea14097e8f0574e9a605..922c3da4e50489ecf614d3493b6f80abb44650ca 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -571,4 +571,19 @@
BUILTIN_GPI (UNOP, fix_truncdf, 2)
BUILTIN_GPI_I16 (UNOPUS, fixuns_trunchf, 2)
BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2)
- BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
\ No newline at end of file
+ BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
+
+ /* Implemented by aarch64_sm3ss1qv4si. */
+ VAR1 (TERNOPU, sm3ss1q, 0, v4si)
+ /* Implemented by aarch64_sm3tt<sm3tt_op>qv4si. */
+ VAR1 (QUADOPUI, sm3tt1aq, 0, v4si)
+ VAR1 (QUADOPUI, sm3tt1bq, 0, v4si)
+ VAR1 (QUADOPUI, sm3tt2aq, 0, v4si)
+ VAR1 (QUADOPUI, sm3tt2bq, 0, v4si)
+ /* Implemented by aarch64_sm3partw<sm3part_op>qv4si. */
+ VAR1 (TERNOPU, sm3partw1q, 0, v4si)
+ VAR1 (TERNOPU, sm3partw2q, 0, v4si)
+ /* Implemented by aarch64_sm4eqv4si. */
+ VAR1 (BINOPU, sm4eq, 0, v4si)
+ /* Implemented by aarch64_sm4ekeyqv4si. */
+ VAR1 (BINOPU, sm4ekeyq, 0, v4si)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 1b61913a13a9f41db7e8f9529e697818e69a26c0..aa297b4886c80520d941c1a6ad43c073fc3324f1 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5863,6 +5863,65 @@
[(set_attr "type" "crypto_sha256_slow")]
)
+;; SM3
+
+(define_insn "aarch64_sm3ss1qv4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=w")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "w")
+ (match_operand:V4SI 2 "register_operand" "w")
+ (match_operand:V4SI 3 "register_operand" "w")]
+ UNSPEC_SM3SS1))]
+ "TARGET_SIMD && TARGET_SM4"
+ "sm3ss1\\t%0.4s, %1.4s, %2.4s, %3.4s"
+ [(set_attr "type" "crypto_sm3")]
+)
+
+
+(define_insn "aarch64_sm3tt<sm3tt_op>qv4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=w")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:V4SI 2 "register_operand" "w")
+ (match_operand:V4SI 3 "register_operand" "w")
+ (match_operand:SI 4 "aarch64_imm2" "Ui2")]
+ CRYPTO_SM3TT))]
+ "TARGET_SIMD && TARGET_SM4"
+ "sm3tt<sm3tt_op>\\t%0.4s, %2.4s, %3.4s[%4]"
+ [(set_attr "type" "crypto_sm3")]
+)
+
+(define_insn "aarch64_sm3partw<sm3part_op>qv4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=w")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:V4SI 2 "register_operand" "w")
+ (match_operand:V4SI 3 "register_operand" "w")]
+ CRYPTO_SM3PART))]
+ "TARGET_SIMD && TARGET_SM4"
+ "sm3partw<sm3part_op>\\t%0.4s, %2.4s, %3.4s"
+ [(set_attr "type" "crypto_sm3")]
+)
+
+;; SM4
+
+(define_insn "aarch64_sm4eqv4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=w")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:V4SI 2 "register_operand" "w")]
+ UNSPEC_SM4E))]
+ "TARGET_SIMD && TARGET_SM4"
+ "sm4e\\t%0.4s, %2.4s"
+ [(set_attr "type" "crypto_sm4")]
+)
+
+(define_insn "aarch64_sm4ekeyqv4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=w")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "w")
+ (match_operand:V4SI 2 "register_operand" "w")]
+ UNSPEC_SM4EKEY))]
+ "TARGET_SIMD && TARGET_SM4"
+ "sm4ekey\\t%0.4s, %1.4s, %2.4s"
+ [(set_attr "type" "crypto_sm4")]
+)
+
;; pmull
(define_insn "aarch64_crypto_pmulldi"
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 0ca2dfd604cbe34ff0612a125bd06b66fb043c4b..68995f621afe4a406e1b7622548c362b0777ab62 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -153,6 +153,7 @@ extern unsigned aarch64_architecture_version;
#define AARCH64_FL_SHA2 (1 << 14) /* Has Crypto SHA2. */
/* ARMv8.4-A architecture extensions. */
#define AARCH64_FL_V8_4 (1 << 15) /* Has ARMv8.4-A features. */
+#define AARCH64_FL_SM4 (1 << 16) /* Has ARMv8.4-A SM3 and SM4. */
/* Has FP and SIMD. */
#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
@@ -186,6 +187,7 @@ extern unsigned aarch64_architecture_version;
#define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES)
#define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2)
#define AARCH64_ISA_V8_4 (aarch64_isa_flags & AARCH64_FL_V8_4)
+#define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4)
/* Crypto is an optional extension to AdvSIMD. */
#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
@@ -196,6 +198,9 @@ extern unsigned aarch64_architecture_version;
/* AES is an optional extension to AdvSIMD. */
#define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO)
+/* SM is an optional extension to AdvSIMD. */
+#define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4)
+
/* CRC instructions that can be enabled through +crc arch extension. */
#define TARGET_CRC32 (AARCH64_ISA_CRC)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 96e740f91a7fb01d201c1badf08199a2a76cb483..2347e6d95a9841863088addb93ad55d972465999 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -31634,6 +31634,73 @@ vdotq_laneq_s32 (int32x4_t __r, int8x16_t __a, int8x16_t __b, const int __index)
}
#pragma GCC pop_options
+#pragma GCC push_options
+#pragma GCC target(("arch=armv8.2-a+sm4"))
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsm3ss1q_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+{
+ return __builtin_aarch64_sm3ss1qv4si_uuuu (__a, __b, __c);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsm3tt1aq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c, const int __imm2)
+{
+ return __builtin_aarch64_sm3tt1aqv4si_uuuus (__a, __b, __c, __imm2);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsm3tt1bq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c, const int __imm2)
+{
+ return __builtin_aarch64_sm3tt1bqv4si_uuuus (__a, __b, __c, __imm2);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsm3tt2aq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c, const int __imm2)
+{
+ return __builtin_aarch64_sm3tt2aqv4si_uuuus (__a, __b, __c, __imm2);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsm3tt2bq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c, const int __imm2)
+{
+ return __builtin_aarch64_sm3tt2bqv4si_uuuus (__a, __b, __c, __imm2);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsm3partw1q_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+{
+ return __builtin_aarch64_sm3partw1qv4si_uuuu (__a, __b, __c);
+}
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsm3partw2q_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+{
+ return __builtin_aarch64_sm3partw2qv4si_uuuu (__a, __b, __c);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsm4eq_u32 (uint32x4_t __a, uint32x4_t __b)
+{
+ return __builtin_aarch64_sm4eqv4si_uuu (__a, __b);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsm4ekeyq_u32 (uint32x4_t __a, uint32x4_t __b)
+{
+ return __builtin_aarch64_sm4ekeyqv4si_uuu (__a, __b);
+}
+
+#pragma GCC pop_options
+
#undef __aarch64_vget_lane_any
#undef __aarch64_vdup_lane_any
diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index af4143ef756464afac29d17f124b436520f90451..a44f4264ab7104b041c53c89515a88f7c876f703 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -139,6 +139,12 @@
A constraint that matches the immediate constant +1."
(match_test "op == const1_rtx"))
+(define_constraint "Ui2"
+ "@internal
+ A constraint that matches the integers 0...3."
+ (and (match_code "const_int")
+ (match_test "(unsigned HOST_WIDE_INT) ival <= 3")))
+
(define_constraint "Ui3"
"@internal
A constraint that matches the integers 0...4."
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 5d7b0f3540f01ba2e29fbae2eb419db6e26c76c2..f355b334e2306d29427119050b77d62dd6431bac 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -361,6 +361,15 @@
UNSPEC_FMINNM ; Used in aarch64-simd.md.
UNSPEC_SDOT ; Used in aarch64-simd.md.
UNSPEC_UDOT ; Used in aarch64-simd.md.
+ UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
+ UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
+ UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
+ UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
+ UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
+ UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
+ UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
+ UNSPEC_SM4E ; Used in aarch64-simd.md.
+ UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
])
;; ------------------------------------------------------------------
@@ -1133,6 +1142,11 @@
(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
+(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
+ UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
+
+(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
+
;; Iterators for atomic operations.
(define_int_iterator ATOMIC_LDOP
@@ -1305,3 +1319,8 @@
(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
+
+(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
+ (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
+
+(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 2eaf0a7630169c3f4c23632d2a90be9ca15680df..e0bd18d91e2cf187cb3a2fd7650112ae027d0b50 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -160,6 +160,12 @@
(and (match_code "const_int")
(match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
+;; The imm2 field is a 2-bit field that only accepts immediates in the
+;; range 0..3.
+(define_predicate "aarch64_imm2"
+ (and (match_code "const_int")
+ (match_test "UINTVAL (op) <= 3")))
+
;; An immediate that fits into 24 bits.
(define_predicate "aarch64_imm24"
(and (match_code "const_int")
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 03e9cdebb7509333a950581b9206a88afe7b2d0b..19aca96774f00e9cff6260763d93e61aced260e0 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -1084,6 +1084,8 @@
crypto_sha256_fast,\
crypto_sha256_slow,\
crypto_pmull,\
+ crypto_sm3,\
+ crypto_sm4,\
coproc"
(const_string "untyped"))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 9c011911d75426448d5f8834cb3048f51f6a318d..e336b62eab7e048f552f9461cecffc82caaf5bc4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14525,6 +14525,9 @@ Enable the Armv8-a aes and pmull crypto extension. This also enables Advanced
SIMD instructions.
@item sha2
Enable the Armv8-a sha2 crypto extension. This also enables Advanced SIMD instructions.
+@item sm4
+Enable the sm3 and sm4 crypto extension. This also enables Advanced SIMD instructions.
+Use of this option with architectures prior to Armv8.2-A is not supported.
@end table
diff --git a/gcc/testsuite/gcc.target/aarch64/sm3_sm4.c b/gcc/testsuite/gcc.target/aarch64/sm3_sm4.c
new file mode 100644
index 0000000000000000000000000000000000000000..b8981e8e767ac4f7a12ff7b758f7d227cc68e2d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sm3_sm4.c
@@ -0,0 +1,78 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.4-a+sm4" } */
+
+#include "arm_neon.h"
+
+uint32x4_t
+test_vsm3ss1q_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+{
+ return vsm3ss1q_u32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "sm3ss1\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+uint32x4_t
+test_vsm3tt1aq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+{
+ return vsm3tt1aq_u32 (a, b, c, 3);
+}
+
+/* { dg-final { scan-assembler-times "sm3tt1a\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[3\\\]" 1 } } */
+
+uint32x4_t
+test_vsm3tt1bq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+{
+ return vsm3tt1bq_u32 (a, b, c, 1);
+}
+
+/* { dg-final { scan-assembler-times "sm3tt1b\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[1\\\]" 1 } } */
+
+uint32x4_t
+test_vsm3tt2aq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+{
+ return vsm3tt2aq_u32 (a, b, c, 2);
+}
+
+/* { dg-final { scan-assembler-times "sm3tt2a\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[2\\\]" 1 } } */
+
+uint32x4_t
+test_vsm3tt2bq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+{
+ return vsm3tt2bq_u32 (a, b, c, 3);
+}
+
+/* { dg-final { scan-assembler-times "sm3tt2b\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[3\\\]" 1 } } */
+
+uint32x4_t
+test_vsm3partw1q_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+{
+ return vsm3partw1q_u32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "sm3partw1\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+uint32x4_t
+test_vsm3partw2q_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+{
+ return vsm3partw2q_u32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "sm3partw2\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+// SM4
+
+uint32x4_t
+test_vsm4eq_u32 (uint32x4_t a, uint32x4_t b)
+{
+ return vsm4eq_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "sm4e\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+uint32x4_t
+test_vsm4ekeyq_u32 (uint32x4_t a, uint32x4_t b)
+{
+ return vsm4ekeyq_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "sm4ekey\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH 3/5][AArch64] Crypto SM4 Support
2018-01-03 17:26 [PATCH 3/5][AArch64] Crypto SM4 Support Michael Collison
@ 2018-01-09 17:57 ` James Greenhalgh
0 siblings, 0 replies; 2+ messages in thread
From: James Greenhalgh @ 2018-01-09 17:57 UTC (permalink / raw)
To: Michael Collison; +Cc: GCC Patches, nd
On Wed, Jan 03, 2018 at 05:25:57PM +0000, Michael Collison wrote:
> Hi All,
>
> This patch adds support for the SM3/SM4 cryptographic instructions added in
> Armv8.4-a. Support for the new instructions is in the form of new ACLE
> intrinsics. A new command line feature modifier, +sm4, is added to enable the
> support.
>
> Test cases were added to verify that the ACLE Intrinsics generate the
> appropriate SM3/SM4 assembly instructions.
>
> Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all
> instructions assembly correctly.
>
> Okay for trunk?
OK.
Thanks,
James
> 2017-11-10 Michael Collison <michael.collison@arm.com>
>
> * config/aarch64/aarch64-builtins.c:
> (aarch64_types_quadopu_imm_qualifiers, TYPES_QUADOPUI): New.
> * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins):
> (__ARM_FEATURE_SM3): Define if TARGET_SM4 is true.
> (__ARM_FEATURE_SM4): Define if TARGET_SM4 is true.
> * config/aarch64/aarch64.h (AARCH64_FL_SM4): New flags.
> (AARCH64_ISA_SM4): New ISA flag.
> (TARGET_SM4): New feature flag for sm4.
> * config/aarch64/aarch64-simd-builtins.def
> (aarch64_sm3ss1qv4si): Ditto.
> (aarch64_sm3tt1aq4si): Ditto.
> (aarch64_sm3tt1bq4si): Ditto.
> (aarch64_sm3tt2aq4si): Ditto.
> (aarch64_sm3tt2bq4si): Ditto.
> (aarch64_sm3partw1qv4si): Ditto.
> (aarch64_sm3partw2qv4si): Ditto.
> (aarch64_sm4eqv4si): Ditto.
> (aarch64_sm4ekeyqv4si): Ditto.
> * config/aarch64/aarch64-simd.md:
> (aarch64_sm3ss1qv4si): Ditto.
> (aarch64_sm3tt<sm3tt_op>qv4si): Ditto.
> (aarch64_sm3partw<sm3part_op>qv4si): Ditto.
> (aarch64_sm4eqv4si): Ditto.
> (aarch64_sm4ekeyqv4si): Ditto.
> * config/aarch64/iterators.md (sm3tt_op): New int iterator.
> (sm3part_op): Ditto.
> (CRYPTO_SM3TT): Ditto.
> (CRYPTO_SM3PART): Ditto.
> (UNSPEC_SM3SS1): New unspec.
> (UNSPEC_SM3TT1A): Ditto.
> (UNSPEC_SM3TT1B): Ditto.
> (UNSPEC_SM3TT2A): Ditto.
> (UNSPEC_SM3TT2B): Ditto.
> (UNSPEC_SM3PARTW1): Ditto.
> (UNSPEC_SM3PARTW2): Ditto.
> (UNSPEC_SM4E): Ditto.
> (UNSPEC_SM4EKEY): Ditto.
> * config/aarch64/constraints.md (Ui2): New constraint.
> * config/aarch64/predicates.md (aarch64_imm2): New predicate.
> * config/arm/types.md (crypto_sm3): New type attribute.
> (crypto_sm4): Ditto.
> * config/aarch64/arm_neon.h (vsm3ss1q_u32): New intrinsic.
> (vsm3tt1aq_u32): Ditto.
> (vsm3tt1bq_u32): Ditto.
> (vsm3tt2aq_u32): Ditto.
> (vsm3tt2bq_u32): Ditto.
> (vsm3partw1q_u32): Ditto.
> (vsm3partw2q_u32): Ditto.
> (vsm4eq_u32): Ditto.
> (vsm4ekeyq_u32): Ditto.
> (doc/invoke.texi): Document new sm4 option.
> gcc.target/aarch64/sm3_sm4.c: New testcase.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2018-01-09 17:57 ` James Greenhalgh
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