* [PATCH 4/5][AArch64] Crypto sha512 and sha3
@ 2018-01-03 17:30 Michael Collison
2018-01-09 18:03 ` James Greenhalgh
0 siblings, 1 reply; 2+ messages in thread
From: Michael Collison @ 2018-01-03 17:30 UTC (permalink / raw)
To: GCC Patches; +Cc: nd
[-- Attachment #1: Type: text/plain, Size: 2504 bytes --]
Hi All,
This patch adds support for the SHA-512 and SHA-3 instructions added in Armv8.4-a. Support for the new instructions is in the form of new ACLE intrinsics. A new command line feature modifier, +sha3, is added to enable the support.
Test cases were added to verify that the ACLE Intrinsics generate the appropriate SHA-512/SHA-3 assembly instructions.
Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all instructions assembly correctly.
Okay for trunk?
2017-11-10 Michael Collison <michael.collison@arm.com>
* config/aarch64/aarch64-builtins.c:
(aarch64_types_ternopu_imm_qualifiers, TYPES_TERNOPUI): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins):
(__ARM_FEATURE_SHA3): Define if TARGET_SHA3 is true.
* config/aarch64/aarch64.h (AARCH64_FL_SHA3): New flags.
(AARCH64_ISA_SHA3): New ISA flag.
(TARGET_SHA3): New feature flag for sha3.
* config/aarch64/iterators.md (sha512_op): New int attribute.
(CRYPTO_SHA512): New int iterator.
(UNSPEC_SHA512H): New unspec.
(UNSPEC_SHA512H2): Ditto.
(UNSPEC_SHA512SU0): Ditto.
(UNSPEC_SHA512SU1): Ditto.
* config/aarch64/aarch64-simd-builtins.def
(aarch64_crypto_sha512hqv2di): New builtin.
(aarch64_crypto_sha512h2qv2di): Ditto.
(aarch64_crypto_sha512su0qv2di): Ditto.
(aarch64_crypto_sha512su1qv2di): Ditto.
(aarch64_eor3qv8hi): Ditto.
(aarch64_rax1qv2di): Ditto.
(aarch64_xarqv2di): Ditto.
(aarch64_bcaxqv8hi): Ditto.
* config/aarch64/aarch64-simd.md:
(aarch64_crypto_sha512h<sha512_op>qv2di): New pattern.
(aarch64_crypto_sha512su0qv2di): Ditto.
(aarch64_crypto_sha512su1qv2di): Ditto.
(aarch64_eor3qv8hi): Ditto.
(aarch64_rax1qv2di): Ditto.
(aarch64_xarqv2di): Ditto.
(aarch64_bcaxqv8hi): Ditto.
* config/aarch64/arm_neon.h (vsha512hq_u64): New intrinsic.
(vsha512h2q_u64): Ditto.
(vsha512su0q_u64): Ditto.
(vsha512su1q_u64): Ditto.
(veor3q_u16): Ditto.
(vrax1q_u64): Ditto.
(vxarq_u64): Ditto.
(vbcaxq_u16): Ditto.
* config/arm/types.md (crypto_sha512): New type attribute.
(crypto_sha3): Ditto.
(doc/invoke.texi): Document new sha3 option.
gcc.target/aarch64/sha2.h: New shared testcase.
gcc.target/aarch64/sha2_1.c: New testcase.
gcc.target/aarch64/sha2_2.c: New testcase.
gcc.target/aarch64/sha2_3.c: New testcase.
gcc.target/aarch64/sha3.h: New shared testcase.
gcc.target/aarch64/sha3_1.c: New testcase.
gcc.target/aarch64/sha3_2.c: New testcase.
gcc.target/aarch64/sha3_3.c: New testcase.
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diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 4d7b5d7b87948b6d997c73a44ab2d294ef494b28..accc4e167e871bac1891d9caa8dc76ad59e95a97 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -162,6 +162,12 @@ aarch64_types_ternopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned,
qualifier_unsigned, qualifier_unsigned };
#define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers)
+static enum aarch64_type_qualifiers
+aarch64_types_ternopu_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_unsigned, qualifier_unsigned,
+ qualifier_unsigned, qualifier_immediate };
+#define TYPES_TERNOPUI (aarch64_types_ternopu_imm_qualifiers)
+
static enum aarch64_type_qualifiers
aarch64_types_quadop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index f02dea58361037ca79a63c481e93fc483922abb6..5770280faba035bf956c934b63b811e2b2aea299 100644
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -137,6 +137,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
aarch64_def_or_undef (TARGET_AES, "__ARM_FEATURE_AES", pfile);
aarch64_def_or_undef (TARGET_SHA2, "__ARM_FEATURE_SHA2", pfile);
+ aarch64_def_or_undef (TARGET_SHA3, "__ARM_FEATURE_SHA3", pfile);
+ aarch64_def_or_undef (TARGET_SHA3, "__ARM_FEATURE_SHA512", pfile);
aarch64_def_or_undef (TARGET_SM4, "__ARM_FEATURE_SM3", pfile);
aarch64_def_or_undef (TARGET_SM4, "__ARM_FEATURE_SM4", pfile);
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index e42c4dff774adbb05a67d61cd23b52db3fa8ce96..a21c037da3f586b422110ced5f509c9b9e225aad 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -39,19 +39,22 @@
that are required. Their order is not important. */
/* Enabling "fp" just enables "fp".
- Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2" and sm3/sm4. */
+ Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2", "sha3", and sm3/sm4. */
AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO |\
- AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SM4, "fp")
+ AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2 |\
+ AARCH64_FL_SHA3 | AARCH64_FL_SM4, "fp")
/* Enabling "simd" also enables "fp".
- Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2" and "sm3/sm4". */
+ Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3" and "sm3/sm4". */
AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, AARCH64_FL_CRYPTO |\
- AARCH64_FL_DOTPROD | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SM4, "asimd")
+ AARCH64_FL_DOTPROD | AARCH64_FL_AES | AARCH64_FL_SHA2 |\
+ AARCH64_FL_SHA3 | AARCH64_FL_SM4, "asimd")
/* Enabling "crypto" also enables "fp" and "simd".
- Disabling "crypto" disables "crypto", "aes", "sha2" and "sm3/sm4". */
+ Disabling "crypto" disables "crypto", "aes", "sha2", "sha3" and "sm3/sm4". */
AARCH64_OPT_EXTENSION("crypto", AARCH64_FL_CRYPTO, AARCH64_FL_FP | AARCH64_FL_SIMD,\
- AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SM4, "aes pmull sha1 sha2")
+ AARCH64_FL_AES | AARCH64_FL_SHA2 |AARCH64_FL_SHA3 | AARCH64_FL_SM4,\
+ "aes pmull sha1 sha2")
/* Enabling or disabling "crc" only changes "crc". */
AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, "crc32")
@@ -82,6 +85,10 @@ AARCH64_OPT_EXTENSION("aes", AARCH64_FL_AES, AARCH64_FL_SIMD, 0, "aes")
Disabling "sha2" just disables "sha2". */
AARCH64_OPT_EXTENSION("sha2", AARCH64_FL_SHA2, AARCH64_FL_SIMD, 0, "sha1 sha2")
+/* Enabling "sha3" enables "simd" and "sha2".
+ Disabling "sha3" just disables "sha3". */
+AARCH64_OPT_EXTENSION("sha3", AARCH64_FL_SHA3, AARCH64_FL_SIMD | AARCH64_FL_SHA2, 0, "sha3 sha512")
+
/* Enabling "sm4" also enables "simd".
Disabling "sm4" just disables "sm4". */
AARCH64_OPT_EXTENSION("sm4", AARCH64_FL_SM4, AARCH64_FL_SIMD, 0, "sm3 sm4")
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 922c3da4e50489ecf614d3493b6f80abb44650ca..8329f8dd8aa45d4d8600718fd2221e55dcac79af 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -587,3 +587,19 @@
VAR1 (BINOPU, sm4eq, 0, v4si)
/* Implemented by aarch64_sm4ekeyqv4si. */
VAR1 (BINOPU, sm4ekeyq, 0, v4si)
+ /* Implemented by aarch64_crypto_sha512hqv2di. */
+ VAR1 (TERNOPU, crypto_sha512hq, 0, v2di)
+ /* Implemented by aarch64_sha512h2qv2di. */
+ VAR1 (TERNOPU, crypto_sha512h2q, 0, v2di)
+ /* Implemented by aarch64_crypto_sha512su0qv2di. */
+ VAR1 (BINOPU, crypto_sha512su0q, 0, v2di)
+ /* Implemented by aarch64_crypto_sha512su1qv2di. */
+ VAR1 (TERNOPU, crypto_sha512su1q, 0, v2di)
+ /* Implemented by aarch64_eor3qv8hi. */
+ VAR1 (TERNOPU, eor3q, 0, v8hi)
+ /* Implemented by aarch64_rax1qv2di. */
+ VAR1 (BINOPU, rax1q, 0, v2di)
+ /* Implemented by aarch64_xarqv2di. */
+ VAR1 (TERNOPUI, xarq, 0, v2di)
+ /* Implemented by aarch64_bcaxqv8hi. */
+ VAR1 (TERNOPU, bcaxq, 0, v8hi)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index aa297b4886c80520d941c1a6ad43c073fc3324f1..6bc0b06748bea777a780f9ee1271594da271c39d 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5863,6 +5863,90 @@
[(set_attr "type" "crypto_sha256_slow")]
)
+;; sha512
+
+(define_insn "aarch64_crypto_sha512h<sha512_op>qv2di"
+ [(set (match_operand:V2DI 0 "register_operand" "=w")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
+ (match_operand:V2DI 2 "register_operand" "w")
+ (match_operand:V2DI 3 "register_operand" "w")]
+ CRYPTO_SHA512))]
+ "TARGET_SIMD && TARGET_SHA3"
+ "sha512h<sha512_op>\\t%q0, %q2, %3.2d"
+ [(set_attr "type" "crypto_sha512")]
+)
+
+(define_insn "aarch64_crypto_sha512su0qv2di"
+ [(set (match_operand:V2DI 0 "register_operand" "=w")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
+ (match_operand:V2DI 2 "register_operand" "w")]
+ UNSPEC_SHA512SU0))]
+ "TARGET_SIMD && TARGET_SHA3"
+ "sha512su0\\t%0.2d, %2.2d"
+ [(set_attr "type" "crypto_sha512")]
+)
+
+(define_insn "aarch64_crypto_sha512su1qv2di"
+ [(set (match_operand:V2DI 0 "register_operand" "=w")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
+ (match_operand:V2DI 2 "register_operand" "w")
+ (match_operand:V2DI 3 "register_operand" "w")]
+ UNSPEC_SHA512SU1))]
+ "TARGET_SIMD && TARGET_SHA3"
+ "sha512su1\\t%0.2d, %2.2d, %3.2d"
+ [(set_attr "type" "crypto_sha512")]
+)
+
+;; sha3
+
+(define_insn "aarch64_eor3qv8hi"
+ [(set (match_operand:V8HI 0 "register_operand" "=w")
+ (xor:V8HI
+ (xor:V8HI
+ (match_operand:V8HI 2 "register_operand" "%w")
+ (match_operand:V8HI 3 "register_operand" "w"))
+ (match_operand:V8HI 1 "register_operand" "w")))]
+ "TARGET_SIMD && TARGET_SHA3"
+ "eor3\\t%0.16b, %1.16b, %2.16b, %3.16b"
+ [(set_attr "type" "crypto_sha3")]
+)
+
+(define_insn "aarch64_rax1qv2di"
+ [(set (match_operand:V2DI 0 "register_operand" "=w")
+ (xor:V2DI
+ (rotate:V2DI
+ (match_operand:V2DI 2 "register_operand" "w")
+ (const_int 1))
+ (match_operand:V2DI 1 "register_operand" "w")))]
+ "TARGET_SIMD && TARGET_SHA3"
+ "rax1\\t%0.2d, %1.2d, %2.2d"
+ [(set_attr "type" "crypto_sha3")]
+)
+
+(define_insn "aarch64_xarqv2di"
+ [(set (match_operand:V2DI 0 "register_operand" "=w")
+ (rotatert:V2DI
+ (xor:V2DI
+ (match_operand:V2DI 1 "register_operand" "%w")
+ (match_operand:V2DI 2 "register_operand" "w"))
+ (match_operand:SI 3 "aarch64_simd_shift_imm_di" "Usd")))]
+ "TARGET_SIMD && TARGET_SHA3"
+ "xar\\t%0.2d, %1.2d, %2.2d, %3"
+ [(set_attr "type" "crypto_sha3")]
+)
+
+(define_insn "aarch64_bcaxqv8hi"
+ [(set (match_operand:V8HI 0 "register_operand" "=w")
+ (xor:V8HI
+ (and:V8HI
+ (not:V8HI (match_operand:V8HI 3 "register_operand" "w"))
+ (match_operand:V8HI 2 "register_operand" "w"))
+ (match_operand:V8HI 1 "register_operand" "w")))]
+ "TARGET_SIMD && TARGET_SHA3"
+ "bcax\\t%0.16b, %1.16b, %2.16b, %3.16b"
+ [(set_attr "type" "crypto_sha3")]
+)
+
;; SM3
(define_insn "aarch64_sm3ss1qv4si"
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 68995f621afe4a406e1b7622548c362b0777ab62..b37f1d58a857afb0ff6320acd234c39abadd0fb8 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -154,6 +154,7 @@ extern unsigned aarch64_architecture_version;
/* ARMv8.4-A architecture extensions. */
#define AARCH64_FL_V8_4 (1 << 15) /* Has ARMv8.4-A features. */
#define AARCH64_FL_SM4 (1 << 16) /* Has ARMv8.4-A SM3 and SM4. */
+#define AARCH64_FL_SHA3 (1 << 17) /* Has ARMv8.4-a SHA3 and SHA512. */
/* Has FP and SIMD. */
#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
@@ -188,6 +189,7 @@ extern unsigned aarch64_architecture_version;
#define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2)
#define AARCH64_ISA_V8_4 (aarch64_isa_flags & AARCH64_FL_V8_4)
#define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4)
+#define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3)
/* Crypto is an optional extension to AdvSIMD. */
#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
@@ -195,6 +197,9 @@ extern unsigned aarch64_architecture_version;
/* SHA2 is an optional extension to AdvSIMD. */
#define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO)
+/* SHA3 is an optional extension to AdvSIMD. */
+#define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3)
+
/* AES is an optional extension to AdvSIMD. */
#define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 2347e6d95a9841863088addb93ad55d972465999..b48299af9da51b4da4456ac58b0e44cd5ba68504 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -31701,6 +31701,66 @@ vsm4ekeyq_u32 (uint32x4_t __a, uint32x4_t __b)
#pragma GCC pop_options
+#pragma GCC push_options
+#pragma GCC target(("arch=armv8.2-a+crypto"))
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsha512hq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
+{
+ return __builtin_aarch64_crypto_sha512hqv2di_uuuu (__a, __b, __c);
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsha512h2q_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
+{
+ return __builtin_aarch64_crypto_sha512h2qv2di_uuuu (__a, __b, __c);
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsha512su0q_u64 (uint64x2_t __a, uint64x2_t __b)
+{
+ return __builtin_aarch64_crypto_sha512su0qv2di_uuu (__a, __b);
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vsha512su1q_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
+{
+ return __builtin_aarch64_crypto_sha512su1qv2di_uuuu (__a, __b, __c);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+veor3q_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
+{
+ return __builtin_aarch64_eor3qv8hi_uuuu (__a, __b, __c);
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vrax1q_u64 (uint64x2_t __a, uint64x2_t __b)
+{
+ return __builtin_aarch64_rax1qv2di_uuu (__a, __b);
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vxarq_u64 (uint64x2_t __a, uint64x2_t __b, const int imm6)
+{
+ return __builtin_aarch64_xarqv2di_uuus (__a, __b,imm6);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vbcaxq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
+{
+ return __builtin_aarch64_bcaxqv8hi_uuuu (__a, __b, __c);
+}
+#pragma GCC pop_options
+
#undef __aarch64_vget_lane_any
#undef __aarch64_vdup_lane_any
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index f355b334e2306d29427119050b77d62dd6431bac..92124dacf953e05a18b191a81e1d4490409dca27 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -370,6 +370,10 @@
UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
UNSPEC_SM4E ; Used in aarch64-simd.md.
UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
+ UNSPEC_SHA512H ; Used in aarch64-simd.md.
+ UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
+ UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
+ UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
])
;; ------------------------------------------------------------------
@@ -1142,6 +1146,8 @@
(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
+(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
+
(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
@@ -1320,6 +1326,8 @@
(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
+(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
+
(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
(UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 19aca96774f00e9cff6260763d93e61aced260e0..9d26a376a43228ff3cb26442b3cab9e720e63e6d 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -1084,6 +1084,8 @@
crypto_sha256_fast,\
crypto_sha256_slow,\
crypto_pmull,\
+ crypto_sha512,\
+ crypto_sha3,\
crypto_sm3,\
crypto_sm4,\
coproc"
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e336b62eab7e048f552f9461cecffc82caaf5bc4..45f00592d754743e62951969713b3797776b2abd 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14525,6 +14525,9 @@ Enable the Armv8-a aes and pmull crypto extension. This also enables Advanced
SIMD instructions.
@item sha2
Enable the Armv8-a sha2 crypto extension. This also enables Advanced SIMD instructions.
+@item sha3
+Enable the sha512 and sha3 crypto extension. This also enables Advanced SIMD
+instructions. Use of this option with architectures prior to Armv8.2-A is not supported.
@item sm4
Enable the sm3 and sm4 crypto extension. This also enables Advanced SIMD instructions.
Use of this option with architectures prior to Armv8.2-A is not supported.
diff --git a/gcc/testsuite/gcc.target/aarch64/sha2.h b/gcc/testsuite/gcc.target/aarch64/sha2.h
new file mode 100644
index 0000000000000000000000000000000000000000..d67c687a077070fae7b8b82faa1546580dceabd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sha2.h
@@ -0,0 +1,25 @@
+#include "arm_neon.h"
+
+uint64x2_t
+test_vsha512hq_u64 (uint64x2_t a, uint64x2_t b, uint64x2_t c)
+{
+ return vsha512hq_u64 (a, b, c);
+}
+
+uint64x2_t
+test_vsha512h2q_u64 (uint64x2_t a, uint64x2_t b, uint64x2_t c)
+{
+ return vsha512h2q_u64 (a, b, c);
+}
+
+uint64x2_t
+test_vsha512su0q_u64 (uint64x2_t a, uint64x2_t b)
+{
+ return vsha512su0q_u64 (a, b);
+}
+
+uint64x2_t
+test_vsha512su1q_u64 (uint64x2_t a, uint64x2_t b, uint64x2_t c)
+{
+ return vsha512su1q_u64 (a, b, c);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/sha2_1.c b/gcc/testsuite/gcc.target/aarch64/sha2_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..55a5d895ec4d49e1cf058c3af170f8ad10c4a9cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sha2_1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.2-a+sha3" } */
+
+#include "sha2.h"
+
+/* { dg-final { scan-assembler-times "sha512h\\tq\[0-9\]+, q\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "sha512h2\\tq\[0-9\]+, q\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "sha512su0\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "sha512su1\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sha2_2.c b/gcc/testsuite/gcc.target/aarch64/sha2_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..5387b92a99048c4f178f19df06f6087e1ada038c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sha2_2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.3-a+sha3" } */
+
+#include "sha2.h"
+
+/* { dg-final { scan-assembler-times "sha512h\\tq\[0-9\]+, q\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "sha512h2\\tq\[0-9\]+, q\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "sha512su0\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "sha512su1\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sha2_3.c b/gcc/testsuite/gcc.target/aarch64/sha2_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..52374c3b257531f0543e9a517e57c620a6ab692c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sha2_3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.4-a+sha3" } */
+
+#include "sha2.h"
+
+/* { dg-final { scan-assembler-times "sha512h\\tq\[0-9\]+, q\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "sha512h2\\tq\[0-9\]+, q\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "sha512su0\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "sha512su1\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sha3.h b/gcc/testsuite/gcc.target/aarch64/sha3.h
new file mode 100644
index 0000000000000000000000000000000000000000..76dd1931dffbf60c521e824a0c5d51d9aa08c9f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sha3.h
@@ -0,0 +1,25 @@
+#include "arm_neon.h"
+
+uint16x8_t
+test_veor3q_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
+{
+ return veor3q_u16 (a, b, c);
+}
+
+uint64x2_t
+test_vrax1q_u64 (uint64x2_t a, uint64x2_t b)
+{
+ return vrax1q_u64 (a, b);
+}
+
+uint64x2_t
+test_vxarq_u64 (uint64x2_t a, uint64x2_t b)
+{
+ return vxarq_u64 (a, b, 15);
+}
+
+uint16x8_t
+test_vbcaxq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
+{
+ return vbcaxq_u16 (a, b, c);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/sha3_1.c b/gcc/testsuite/gcc.target/aarch64/sha3_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..879eadd875e899c70b32680d40bdb3de419f00a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sha3_1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.2-a+sha3" } */
+
+#include "sha3.h"
+
+
+/* { dg-final { scan-assembler-times "eor3\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "rax1\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "xar\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d, 15" 1 } } */
+/* { dg-final { scan-assembler-times "bcax\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sha3_2.c b/gcc/testsuite/gcc.target/aarch64/sha3_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..2afe28c47445af53194427912b9d6a9de9b5ff04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sha3_2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.3-a+sha3" } */
+
+#include "sha3.h"
+
+/* { dg-final { scan-assembler-times "eor3\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "rax1\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "xar\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d, 15" 1 } } */
+/* { dg-final { scan-assembler-times "bcax\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sha3_3.c b/gcc/testsuite/gcc.target/aarch64/sha3_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..8915c805c3e55cb46691602dcf6a3627a28cb3c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sha3_3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.4-a+sha3" } */
+
+#include "sha3.h"
+
+/* { dg-final { scan-assembler-times "eor3\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "rax1\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "xar\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d, 15" 1 } } */
+/* { dg-final { scan-assembler-times "bcax\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH 4/5][AArch64] Crypto sha512 and sha3
2018-01-03 17:30 [PATCH 4/5][AArch64] Crypto sha512 and sha3 Michael Collison
@ 2018-01-09 18:03 ` James Greenhalgh
0 siblings, 0 replies; 2+ messages in thread
From: James Greenhalgh @ 2018-01-09 18:03 UTC (permalink / raw)
To: Michael Collison; +Cc: GCC Patches, nd
On Wed, Jan 03, 2018 at 05:30:33PM +0000, Michael Collison wrote:
> Hi All,
>
> This patch adds support for the SHA-512 and SHA-3 instructions added in
> Armv8.4-a. Support for the new instructions is in the form of new ACLE
> intrinsics. A new command line feature modifier, +sha3, is added to enable
> the support.
>
> Test cases were added to verify that the ACLE Intrinsics generate the
> appropriate SHA-512/SHA-3 assembly instructions.
>
> Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all
> instructions assembly correctly.
>
> Okay for trunk?
OK.
Thanks,
James
>
> 2017-11-10 Michael Collison <michael.collison@arm.com>
>
> * config/aarch64/aarch64-builtins.c:
> (aarch64_types_ternopu_imm_qualifiers, TYPES_TERNOPUI): New.
> * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins):
> (__ARM_FEATURE_SHA3): Define if TARGET_SHA3 is true.
> * config/aarch64/aarch64.h (AARCH64_FL_SHA3): New flags.
> (AARCH64_ISA_SHA3): New ISA flag.
> (TARGET_SHA3): New feature flag for sha3.
> * config/aarch64/iterators.md (sha512_op): New int attribute.
> (CRYPTO_SHA512): New int iterator.
> (UNSPEC_SHA512H): New unspec.
> (UNSPEC_SHA512H2): Ditto.
> (UNSPEC_SHA512SU0): Ditto.
> (UNSPEC_SHA512SU1): Ditto.
> * config/aarch64/aarch64-simd-builtins.def
> (aarch64_crypto_sha512hqv2di): New builtin.
> (aarch64_crypto_sha512h2qv2di): Ditto.
> (aarch64_crypto_sha512su0qv2di): Ditto.
> (aarch64_crypto_sha512su1qv2di): Ditto.
> (aarch64_eor3qv8hi): Ditto.
> (aarch64_rax1qv2di): Ditto.
> (aarch64_xarqv2di): Ditto.
> (aarch64_bcaxqv8hi): Ditto.
> * config/aarch64/aarch64-simd.md:
> (aarch64_crypto_sha512h<sha512_op>qv2di): New pattern.
> (aarch64_crypto_sha512su0qv2di): Ditto.
> (aarch64_crypto_sha512su1qv2di): Ditto.
> (aarch64_eor3qv8hi): Ditto.
> (aarch64_rax1qv2di): Ditto.
> (aarch64_xarqv2di): Ditto.
> (aarch64_bcaxqv8hi): Ditto.
> * config/aarch64/arm_neon.h (vsha512hq_u64): New intrinsic.
> (vsha512h2q_u64): Ditto.
> (vsha512su0q_u64): Ditto.
> (vsha512su1q_u64): Ditto.
> (veor3q_u16): Ditto.
> (vrax1q_u64): Ditto.
> (vxarq_u64): Ditto.
> (vbcaxq_u16): Ditto.
> * config/arm/types.md (crypto_sha512): New type attribute.
> (crypto_sha3): Ditto.
> (doc/invoke.texi): Document new sha3 option.
> gcc.target/aarch64/sha2.h: New shared testcase.
> gcc.target/aarch64/sha2_1.c: New testcase.
> gcc.target/aarch64/sha2_2.c: New testcase.
> gcc.target/aarch64/sha2_3.c: New testcase.
> gcc.target/aarch64/sha3.h: New shared testcase.
> gcc.target/aarch64/sha3_1.c: New testcase.
> gcc.target/aarch64/sha3_2.c: New testcase.
> gcc.target/aarch64/sha3_3.c: New testcase.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2018-01-09 18:03 ` James Greenhalgh
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