From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 118038 invoked by alias); 4 Sep 2018 17:20:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 117997 invoked by uid 89); 4 Sep 2018 17:20:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1888 X-HELO: EUR02-HE1-obe.outbound.protection.outlook.com Received: from mail-eopbgr10055.outbound.protection.outlook.com (HELO EUR02-HE1-obe.outbound.protection.outlook.com) (40.107.1.55) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 04 Sep 2018 17:20:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BqqciO9tDalnJZej2HIY98rQhD4NtTyIiEwXfqw4P20=; b=ltWv7Ll9eSlyY1+VDLNeXBeZ+iX0ZNwmSs40hFrn+LTjVYoHtlnv1JaBYge48tBCDgd+xoZhJSohshLR8IUJ6fkrQGTE6b3DvG+9kuiLf07QiJTSAemldgUGcw2Pyr/awIGbPjlCTgovvVupoBeye9uPLgn79me+gOE46O1U98Y= Received: from DB5PR08MB1030.eurprd08.prod.outlook.com (10.166.14.15) by DB5PR08MB0327.eurprd08.prod.outlook.com (10.161.241.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1101.17; Tue, 4 Sep 2018 17:20:16 +0000 Received: from DB5PR08MB1030.eurprd08.prod.outlook.com ([fe80::6136:7a10:5f2:7593]) by DB5PR08MB1030.eurprd08.prod.outlook.com ([fe80::6136:7a10:5f2:7593%3]) with mapi id 15.20.1101.016; Tue, 4 Sep 2018 17:20:16 +0000 From: Wilco Dijkstra To: Kyrill Tkachov , "sellcey@cavium.com" , Segher Boessenkool CC: gcc-patches , Richard Sandiford , Richard Earnshaw , James Greenhalgh , Marcus Shawcroft , nd Subject: Re: [Patch][Aarch64] Implement Aarch64 SIMD ABI and aarch64_vector_pcs attribute Date: Tue, 04 Sep 2018 17:20:00 -0000 Message-ID: References: <1533075888.3879.14.camel@cavium.com> <5B61A40E.1040501@foss.arm.com> <1533593632.3879.90.camel@cavium.com> <20180807171509.GH31204@gate.crashing.org> <1534786623.20144.12.camel@cavium.com>,<5B8E6EA3.6020704@foss.arm.com>, In-Reply-To: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-SW-Source: 2018-09/txt/msg00212.txt.bz2 Hi Steve, The latest version compiles the examples I used correctly, so it looks fine from that perspective (but see comments below). However the key point of=20 the ABI is to enable better code generation when calling a vector function, and that will likely require further changes that may conflict with this pa= tch. Do you have patches for that work outstanding? It seems best to do this in one go. Also did you check there is no regression in code generation for non-vector functions?=20 +/* Return 1 if the register is used by the epilogue.=A0 We need to say the +=A0=A0 return register is used, but only after epilogue generation is comp= lete. +=A0=A0 Note that in the case of sibcalls, the values "used by the epilogue= " are +=A0=A0 considered live at the start of the called function. + +=A0=A0 For SIMD functions we need to return 1 for FP registers that are sa= ved and +=A0=A0 restored by a function but not zero in call_used_regs.=A0 If we do = not do=20 +=A0=A0 this optimizations may remove the restore of the register.=A0 */ + +int +aarch64_epilogue_uses (int regno) +{ +=A0 if (epilogue_completed && (regno) =3D=3D LR_REGNUM) +=A0=A0=A0 return 1; +=A0 if (aarch64_simd_decl_p (cfun->decl) && FP_SIMD_SAVED_REGNUM_P (regno)) +=A0=A0=A0 return 1; +=A0 return 0; +} I'm not convinced this is a good idea. It suggests GCC doesn't have the cor= rect set of caller/callee-save registers for vector functions (I don't see a change = to update CALL_USED_REGISTERS or aarch64_hard_regno_call_part_clobbered), which could lead to all kinds of interesting issues. +/* Return false for non-leaf SIMD functions in order to avoid +=A0=A0 shrink-wrapping them.=A0 Doing this will lose the necessary +=A0=A0 save/restore of FP registers.=A0 */ + +bool +aarch64_use_simple_return_insn_p (void) +{ +=A0 if (aarch64_simd_decl_p (cfun->decl) && !crtl->is_leaf) +=A0=A0=A0 return false; + +=A0 return true; +} Such as this... Wilco =20=20=20=20