Re: [PATCH][AArch64] Add BIC-imm and ORR-imm SIMD pattern

[Sudi Das <Sudi.Das@arm.com>]

Hi Steve

Sorry about this.
I am on it. I have a fix and I am running tests on it right now.

Sudi


From: Steve Ellcey <sellcey@cavium.com>
Sent: Thursday, October 5, 2017 12:05 AM
To: Richard Earnshaw; Sudi Das; James Greenhalgh
Cc: gcc-patches@gcc.gnu.org; nd; Marcus Shawcroft
Subject: Re: [PATCH][AArch64] Add BIC-imm and ORR-imm SIMD pattern
    
On Wed, 2017-10-04 at 16:41 +0100, Richard Earnshaw (lists) wrote:
> On 02/10/17 10:05, Sudi Das wrote:
> > 
> > 2017-10-02 Sudakshina Das  <sudi.das@arm.com>
> > 
> >      * config/aarch64/aarch64-protos.h (enum simd_immediate_check): New check type
> >      for aarch64_simd_valid_immediate.
> >      (aarch64_output_simd_mov_immediate): Update prototype.
> >      (aarch64_simd_valid_immediate): Update prototype.
> > 
> >      * config/aarch64/aarch64-simd.md (orr<mode>3): modified pattern to add
> >      support for ORR-immediate.
> >      (and<mode>3): modified pattern to add support for BIC-immediate.
> > 
> >      * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Function now checks
> >      for valid immediate for BIC and ORR based on new enum argument.
> >      (aarch64_output_simd_mov_immediate): Function now used to output BIC/ORR imm
> >      as well based on new enum argument.
> >  
> >      * config/aarch64/constraints.md (Do): New vector immediate constraint.
> >      (Db) : Likewise.
> > 
> >      * config/aarch64/predicates.md (aarch64_reg_or_orr_imm): New
> > predicate.
> >      (aarch64_reg_or_bic_imm): Likewise.

I think this patch is causing a bunch of test failures on aarch64.  I
had to apply the patch for PR82396 (that was reverted) in order to
build ToT GCC, but when I did that and ran the testsuite I got a bunch
of failures like:

/home/sellcey/cavium-pr-27386/src/gcc/gcc/testsuite/gcc.c-
torture/compile/pr54713-1.c:45:18: internal compiler error: in
aarch64_simd_valid_immediate, at config/aarch64/aarch64.c:11539
0xf2227b aarch64_simd_valid_immediate(rtx_def*, machine_mode, bool,
simd_immediate_info*, simd_immediate_check)
        ../../../src/gcc/gcc/config/aarch64/aarch64.c:11539
0x11047b3 aarch64_reg_or_bic_imm(rtx_def*, machine_mode)
        ../../../src/gcc/gcc/config/aarch64/predicates.md:79
0xab29ab insn_operand_matches(insn_code, unsigned int, rtx_def*)
        ../../../src/gcc/gcc/optabs.c:6891
0xab29ab maybe_legitimize_operand_same_code
        ../../../src/gcc/gcc/optabs.c:6919
0xab545f maybe_legitimize_operand
        ../../../src/gcc/gcc/optabs.c:6990
0xab545f maybe_legitimize_operands(insn_code, unsigned int, unsigned
int, expand_operand*)
        ../../../src/gcc/gcc/optabs.c:7055
0xab5a8f maybe_gen_insn(insn_code, unsigned int, expand_operand*)
        ../../../src/gcc/gcc/optabs.c:7073
0xab8503 expand_binop_directly
        ../../../src/gcc/gcc/optabs.c:1075
0xab87af expand_binop(machine_mode, optab_tag, rtx_def*, rtx_def*,
rtx_def*, int, optab_methods)
        ../../../src/gcc/gcc/optabs.c:1156
0x8736d7 expand_expr_real_2(separate_ops*, rtx_def*, machine_mode,
expand_modifier)
        ../../../src/gcc/gcc/expr.c:9582
0x749027 expand_gimple_stmt_1
        ../../../src/gcc/gcc/cfgexpand.c:3691
0x749027 expand_gimple_stmt
        ../../../src/gcc/gcc/cfgexpand.c:3751
0x750387 expand_gimple_basic_block
        ../../../src/gcc/gcc/cfgexpand.c:5750
0x751ef7 execute
        ../../../src/gcc/gcc/cfgexpand.c:6357