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received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7a93ce4b-a7d2-4f05-3afe-08d535aa6505 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Nov 2017 15:20:29.7253 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR08MB2664 X-SW-Source: 2017-11/txt/msg02305.txt.bz2 The recently added store_pair_lanes causes ICEs in output_operand. This is due to aarch64_classify_address treating it like a 128-bit STR rather than a STP. The valid immediate offsets don't fully overlap, causing it to return false. Eg. offset 264 is a valid 8-byte STP offset but not a valid 16-byte STR offset since it isn't a multiple of 16. The original instruction isn't passed in the printing code, so the context is unclear. The solution is to add a new operand formatting specifier which is used for LDP/STP instructions like this. This, like the Uml constraint that applies to store_pair_lanes, uses PARALLEL when calling aarch64_classify_address so that it knows it is an STP. Also add the 'z' specifier for future use by load/store pair instructions. Passes regress, OK for commit?=20 ChangeLog: 2017-11-27 Wilco Dijkstra * config/aarch64/aarch64.c (aarch64_print_operand): Add new cases for printing LDP/STP memory addresses. (aarch64_print_address_internal): Renamed from aarch64_print_operand_address, added parameter, add Pmode check. (aarch64_print_ldpstp_address): New function for LDP/STP addresses. (aarch64_print_operand_address): Indirect to aarch64_print_address_internal. * config/aarch64/aarch64-simd.md (store_pair_lanes): Use new 'y' operand output specifier. -- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch6= 4-simd.md index cddd935d96589c52519334bd1b8c24e80ea475f3..b7dfbfaa1b00df113329e4b3539= 7e2b6ce234786 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3047,8 +3047,8 @@ (define_insn "store_pair_lanes" (match_operand:VDC 2 "register_operand" "w, r")))] "TARGET_SIMD" "@ - stp\\t%d1, %d2, %0 - stp\\t%x1, %x2, %0" + stp\\t%d1, %d2, %y0 + stp\\t%x1, %x2, %y0" [(set_attr "type" "neon_stp, store_16")] ) =20 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 60a8555b16296f07c68059bc54db803aeef0f369..e601f573bde4fae9a6e32af79ee= 987190895e088 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -150,6 +150,7 @@ static bool aarch64_builtin_support_vector_misalignment= (machine_mode mode, bool is_packed); static machine_mode aarch64_simd_container_mode (scalar_mode mode, unsigned width); +static void aarch64_print_ldpstp_address (FILE *f, machine_mode mode, rtx = x); =20 /* Major revision number of the ARM Architecture implemented by the target= . */ unsigned aarch64_architecture_version; @@ -5448,7 +5449,11 @@ static const int aarch64_nzcv_codes[] =3D 'L': Output constant address specified by X with a relocation offset if appropriate. 'G': Prints address of X, specifying a PC relative - relocation mode if appropriate. */ + relocation mode if appropriate. + 'y': Output address of LDP or STP - this is used for + some LDP/STPs which don't use a PARALLEL in their + pattern (so the mode needs to be adjusted). + 'z': Output address of a typical LDP or STP. */ =20 static void aarch64_print_operand (FILE *f, rtx x, int code) @@ -5650,8 +5655,6 @@ aarch64_print_operand (FILE *f, rtx x, int code) =20 case MEM: output_address (GET_MODE (x), XEXP (x, 0)); - /* Check all memory references are Pmode - even with ILP32. */ - gcc_assert (GET_MODE (XEXP (x, 0)) =3D=3D Pmode); break; =20 case CONST: @@ -5815,18 +5818,48 @@ aarch64_print_operand (FILE *f, rtx x, int code) } break; =20 + case 'y': + case 'z': + { + machine_mode mode =3D GET_MODE (x); + + if (GET_CODE (x) !=3D MEM) + { + output_operand_lossage ("invalid operand for '%%%c'", code); + return; + } + + if (code =3D=3D 'y') + { + /* LDP/STP which uses a single double-width memory operand. + Adjust the mode to appear like a typical LDP/STP. + Currently this is supported for 16-byte accesses only. */ + gcc_assert (GET_MODE_SIZE (mode) =3D=3D 16); + mode =3D DFmode; + } + + aarch64_print_ldpstp_address (f, mode, XEXP (x, 0)); + } + break; + default: output_operand_lossage ("invalid operand prefix '%%%c'", code); return; } } =20 +/* Print address 'x' of a memory access with mode 'mode'. + 'op' is the context required by aarch64_classify_address. It can eithe= r be + MEM for a normal memory access or PARALLEL for LDP/STP. */ static void -aarch64_print_operand_address (FILE *f, machine_mode mode, rtx x) +aarch64_print_address_internal (FILE *f, machine_mode mode, rtx x, RTX_COD= E op) { struct aarch64_address_info addr; =20 - if (aarch64_classify_address (&addr, x, mode, MEM, true)) + /* Check all addresses are Pmode - including ILP32. */ + gcc_assert (GET_MODE (x) =3D=3D Pmode); + + if (aarch64_classify_address (&addr, x, mode, op, true)) switch (addr.type) { case ADDRESS_REG_IMM: @@ -5909,6 +5942,20 @@ aarch64_print_operand_address (FILE *f, machine_mode= mode, rtx x) output_addr_const (f, x); } =20 +/* Print address 'x' of a LDP/STP with mode 'mode'. */ +static void +aarch64_print_ldpstp_address (FILE *f, machine_mode mode, rtx x) +{ + aarch64_print_address_internal (f, mode, x, PARALLEL); +} + +/* Print address 'x' of a memory access with mode 'mode'. */ +static void +aarch64_print_operand_address (FILE *f, machine_mode mode, rtx x) +{ + aarch64_print_address_internal (f, mode, x, MEM); +} + bool aarch64_label_mentioned_p (rtx x) {