Hi all, There was previously no backend pattern to utilise the scvtf fbits option. Where a fixed point is converted to a float, and divided by a power of 2, (or multiplied by the reciprocal of a power of 2), this can be combined into a single scvtf with fbits operation. This patch adds a pattern to combine these instructions, and adds a helper function. For the following test case: float f(int a) { return ((float) a) / 65536.0; } double g(int a) { return ((double) a) / 4096.0; } the output generated is currently: f: scvtf s1, w0 // 6 [c=8 l=4] floatsisf2/1 mov w1, 931135488 // 17 [c=4 l=4] *movsi_aarch64/3 fmov s0, w1 // 18 [c=4 l=4] *movsf_aarch64/1 fmul s0, s1, s0 // 13 [c=8 l=4] mulsf3 ret // 24 [c=0 l=4] *do_return g: scvtf d1, w0 // 6 [c=8 l=4] floatsidf2 mov x1, 4553139223271571456 // 17 [c=4 l=4] *movdi_aarch64/3 fmov d0, x1 // 18 [c=4 l=4] *movdf_aarch64/1 fmul d0, d1, d0 // 13 [c=8 l=4] muldf3 ret // 24 [c=0 l=4] *do_return The output with this patch applied is: f: scvtf s0, w0, #16 // 13 [c=24 l=4] *combine_scvtf_SI_sf3/1 ret // 22 [c=0 l=4] *do_return g: scvtf d0, w0, #12 // 13 [c=24 l=4] *combine_scvtf_SI_df3 ret // 22 [c=0 l=4] *do_return gcc/ChangeLog: 2019-06-12 Joel Hutton * config/aarch64/aarch64-protos.h (aarch64_fpconst_pow2_recip): New prototype * config/aarch64/aarch64.c (aarch64_fpconst_pow2_recip): New function * config/aarch64/aarch64.md (*aarch64_cvtf__2_mult): New pattern (aarch64_cvtf__2_mult): New pattern * config/aarch64/constraints.md (Dt): New constraint * config/aarch64/predicates.md (aarch64_fpconst_pow2_recip): New predicate gcc/testsuite/ChangeLog: 2019-06-12 Joel Hutton * gcc.target/aarch64/fmul_scvtf.c: New test. Bootstrapped and regression tested on aarch64-linux-none target.