[PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[Andrea Corallo]

[-- Attachment #1: Type: text/plain, Size: 323 bytes --]

Hi all,

I'd like to submit the following patch implementing the bfloat16_t
neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16.

Please see refer to:
ACLE <https://developer.arm.com/docs/101028/latest>
ISA  <https://developer.arm.com/docs/ddi0596/latest>

Regtested and bootstrapped.

Okay for trunk?

  Andrea


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From 64e375906abeba1ab14d06106a9714b0371b7105 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Wed, 21 Oct 2020 11:16:01 +0200
Subject: [PATCH] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

gcc/ChangeLog

2020-10-21  Andrea Corallo  <andrea.corallo@arm.com>

	* config/arm/arm_neon_builtins.def: Add to LOAD1LANE v4bf, v8bf.
	* config/arm/arm_neon.h (vld1_lane_bf16, vld1q_lane_bf16): Add
	intrinsics.

gcc/testsuite/ChangeLog

2020-10-21  Andrea Corallo  <andrea.corallo@arm.com>

	* gcc.target/arm/simd/vld1_lane_bf16_1.c: New testcase.
	* gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
	* gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
---
 gcc/config/arm/arm_neon.h                     | 14 +++++++++++++
 gcc/config/arm/arm_neon_builtins.def          |  4 ++--
 .../gcc.target/arm/simd/vld1_lane_bf16_1.c    | 21 +++++++++++++++++++
 .../arm/simd/vld1_lane_bf16_indices_1.c       | 17 +++++++++++++++
 .../arm/simd/vld1q_lane_bf16_indices_1.c      | 17 +++++++++++++++
 5 files changed, 71 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index aa21730dea0..fcd8020425e 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -19665,6 +19665,20 @@ vld4q_dup_bf16 (const bfloat16_t * __ptr)
   return __rv.__i;
 }
 
+__extension__ extern __inline bfloat16x4_t
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_lane_bf16 (const bfloat16_t * __a, bfloat16x4_t __b, const int __c)
+{
+  return __builtin_neon_vld1_lanev4bf (__a, __b, __c);
+}
+
+__extension__ extern __inline bfloat16x8_t
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_lane_bf16 (const bfloat16_t * __a, bfloat16x8_t __b, const int __c)
+{
+  return __builtin_neon_vld1_lanev8bf (__a, __b, __c);
+}
+
 #pragma GCC pop_options
 
 #ifdef __cplusplus
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 34c1945c0a1..7cdcd251243 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -312,8 +312,8 @@ VAR1 (TERNOP, vtbx3, v8qi)
 VAR1 (TERNOP, vtbx4, v8qi)
 VAR12 (LOAD1, vld1,
         v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
-VAR10 (LOAD1LANE, vld1_lane,
-	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+VAR12 (LOAD1LANE, vld1_lane,
+        v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di, v4bf, v8bf)
 VAR10 (LOAD1, vld1_dup,
 	v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
 VAR12 (STORE1, vst1,
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
new file mode 100644
index 00000000000..fa4e45b7217
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-O3 --save-temps" } */
+
+#include "arm_neon.h"
+
+bfloat16x4_t
+test_vld1_lane_bf16 (bfloat16_t *a, bfloat16x4_t b)
+{
+  return vld1_lane_bf16 (a, b, 1);
+}
+
+bfloat16x8_t
+test_vld1q_lane_bf16 (bfloat16_t *a, bfloat16x8_t b)
+{
+  return vld1q_lane_bf16 (a, b, 2);
+}
+
+/* { dg-final { scan-assembler "vld1.16\t{d0\\\[1\\\]}, \\\[r0\\\]" } } */
+/* { dg-final { scan-assembler "vld1.16\t{d0\\\[2\\\]}, \\\[r0\\\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
new file mode 100644
index 00000000000..c83eb53234d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+
+#include "arm_neon.h"
+
+bfloat16x4_t
+test_vld1_lane_bf16 (bfloat16_t *a, bfloat16x4_t b)
+{
+  bfloat16x4_t res;
+  res = vld1_lane_bf16 (a, b, -1);
+  res = vld1_lane_bf16 (a, b, 4);
+  return res;
+}
+
+/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
new file mode 100644
index 00000000000..8e21e61c9c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+
+#include "arm_neon.h"
+
+bfloat16x8_t
+test_vld1q_lane_bf16 (bfloat16_t *a, bfloat16x8_t b)
+{
+  bfloat16x8_t res;
+  res = vld1q_lane_bf16 (a, b, -1);
+  res = vld1q_lane_bf16 (a, b, 8);
+  return res;
+}
+
+/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
-- 
2.20.1

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[Andrea Corallo]

Andrea Corallo via Gcc-patches <gcc-patches@gcc.gnu.org> writes:

> Hi all,
>
> I'd like to submit the following patch implementing the bfloat16_t
> neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16.
>
> Please see refer to:
> ACLE <https://developer.arm.com/docs/101028/latest>
> ISA  <https://developer.arm.com/docs/ddi0596/latest>
>
> Regtested and bootstrapped.
>
> Okay for trunk?
>
>   Andrea

Ping

RE: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[Kyrylo Tkachov]

Hi Andrea,

> -----Original Message-----
> From: Andrea Corallo <Andrea.Corallo@arm.com>
> Sent: 26 October 2020 15:59
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; nd <nd@arm.com>
> Subject: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics
> 
> Hi all,
> 
> I'd like to submit the following patch implementing the bfloat16_t
> neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16.
> 
> Please see refer to:
> ACLE <https://developer.arm.com/docs/101028/latest>
> ISA  <https://developer.arm.com/docs/ddi0596/latest>
> 
> Regtested and bootstrapped.
> 
> Okay for trunk?

Ok.
Thanks,
Kyrill


> 
>   Andrea

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[Christophe Lyon]

On Tue, 3 Nov 2020 at 11:27, Kyrylo Tkachov via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Hi Andrea,
>
> > -----Original Message-----
> > From: Andrea Corallo <Andrea.Corallo@arm.com>
> > Sent: 26 October 2020 15:59
> > To: gcc-patches@gcc.gnu.org
> > Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> > <Richard.Earnshaw@arm.com>; nd <nd@arm.com>
> > Subject: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics
> >
> > Hi all,
> >
> > I'd like to submit the following patch implementing the bfloat16_t
> > neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16.
> >
> > Please see refer to:
> > ACLE <https://developer.arm.com/docs/101028/latest>
> > ISA  <https://developer.arm.com/docs/ddi0596/latest>
> >
> > Regtested and bootstrapped.
> >
> > Okay for trunk?
>

I think you need to add -mfloat-abi=hard to the dg-additional-options
otherwise vld1_lane_bf16_1.c
fails on targets with a soft float-abi default (eg arm-linux-gnueabi).

See bf16_vldn_1.c.

BTW, why did you use a different naming scheme for the tests?
(bf16_vldn_1.c vs vld1_lane_bf16_1.c)

Christophe

> Ok.
> Thanks,
> Kyrill
>
>
> >
> >   Andrea
>

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[Christophe Lyon]

On Wed, 4 Nov 2020 at 14:29, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>
> On Tue, 3 Nov 2020 at 11:27, Kyrylo Tkachov via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > Hi Andrea,
> >
> > > -----Original Message-----
> > > From: Andrea Corallo <Andrea.Corallo@arm.com>
> > > Sent: 26 October 2020 15:59
> > > To: gcc-patches@gcc.gnu.org
> > > Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> > > <Richard.Earnshaw@arm.com>; nd <nd@arm.com>
> > > Subject: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics
> > >
> > > Hi all,
> > >
> > > I'd like to submit the following patch implementing the bfloat16_t
> > > neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16.
> > >
> > > Please see refer to:
> > > ACLE <https://developer.arm.com/docs/101028/latest>
> > > ISA  <https://developer.arm.com/docs/ddi0596/latest>
> > >
> > > Regtested and bootstrapped.
> > >
> > > Okay for trunk?
> >
>
> I think you need to add -mfloat-abi=hard to the dg-additional-options
> otherwise vld1_lane_bf16_1.c
> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>
> See bf16_vldn_1.c.

Actually that's not sufficient because in turn we get:
/sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
error: gnu/stubs-hard.h: No such file or directory

So you should check that -mfloat-abi=hard is supported.

Ditto for the vst tests.

>
> BTW, why did you use a different naming scheme for the tests?
> (bf16_vldn_1.c vs vld1_lane_bf16_1.c)
>
> Christophe
>
> > Ok.
> > Thanks,
> > Kyrill
> >
> >
> > >
> > >   Andrea
> >

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[Andrea Corallo]

Christophe Lyon <christophe.lyon@linaro.org> writes:

> On Wed, 4 Nov 2020 at 14:29, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>
>> On Tue, 3 Nov 2020 at 11:27, Kyrylo Tkachov via Gcc-patches
>> <gcc-patches@gcc.gnu.org> wrote:
>> >
>> > Hi Andrea,
>> >
>> > > -----Original Message-----
>> > > From: Andrea Corallo <Andrea.Corallo@arm.com>
>> > > Sent: 26 October 2020 15:59
>> > > To: gcc-patches@gcc.gnu.org
>> > > Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
>> > > <Richard.Earnshaw@arm.com>; nd <nd@arm.com>
>> > > Subject: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics
>> > >
>> > > Hi all,
>> > >
>> > > I'd like to submit the following patch implementing the bfloat16_t
>> > > neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16.
>> > >
>> > > Please see refer to:
>> > > ACLE <https://developer.arm.com/docs/101028/latest>
>> > > ISA  <https://developer.arm.com/docs/ddi0596/latest>
>> > >
>> > > Regtested and bootstrapped.
>> > >
>> > > Okay for trunk?
>> >
>>
>> I think you need to add -mfloat-abi=hard to the dg-additional-options
>> otherwise vld1_lane_bf16_1.c
>> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>>
>> See bf16_vldn_1.c.
>
> Actually that's not sufficient because in turn we get:
> /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
> error: gnu/stubs-hard.h: No such file or directory
>
> So you should check that -mfloat-abi=hard is supported.
>
> Ditto for the vst tests.
>

Hi Christophe,

thanks for catching this, I'll prepare a patch.

  Andrea

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

[Andrea Corallo]

Christophe Lyon <christophe.lyon@linaro.org> writes:

> On Tue, 3 Nov 2020 at 11:27, Kyrylo Tkachov via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
>>
>> Hi Andrea,
>>
>> > -----Original Message-----
>> > From: Andrea Corallo <Andrea.Corallo@arm.com>
>> > Sent: 26 October 2020 15:59
>> > To: gcc-patches@gcc.gnu.org
>> > Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
>> > <Richard.Earnshaw@arm.com>; nd <nd@arm.com>
>> > Subject: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics
>> >
>> > Hi all,
>> >
>> > I'd like to submit the following patch implementing the bfloat16_t
>> > neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16.
>> >
>> > Please see refer to:
>> > ACLE <https://developer.arm.com/docs/101028/latest>
>> > ISA  <https://developer.arm.com/docs/ddi0596/latest>
>> >
>> > Regtested and bootstrapped.
>> >
>> > Okay for trunk?
>>
>
> I think you need to add -mfloat-abi=hard to the dg-additional-options
> otherwise vld1_lane_bf16_1.c
> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>
> See bf16_vldn_1.c.
>
> BTW, why did you use a different naming scheme for the tests?
> (bf16_vldn_1.c vs vld1_lane_bf16_1.c)

Nothing special, it made more sense to me to use directly the name of
the intrinsic as it include already the bf16 information.  I believe we
have both schemas in the aarch64 & arm backends.  I've no problem with
renaming the tests if we feel is important.

  Andrea

[PATCH] arm: [testcase] Better narrow some bfloat16 testcase

[Andrea Corallo]

[-- Attachment #1: Type: text/plain, Size: 781 bytes --]

Christophe Lyon <christophe.lyon@linaro.org> writes:

[...]

>> I think you need to add -mfloat-abi=hard to the dg-additional-options
>> otherwise vld1_lane_bf16_1.c
>> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>>
>> See bf16_vldn_1.c.
>
> Actually that's not sufficient because in turn we get:
> /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
> error: gnu/stubs-hard.h: No such file or directory
>
> So you should check that -mfloat-abi=hard is supported.
>
> Ditto for the vst tests.

Hi Christophe,

this patch should implement your suggestions.

On my arm-none-linux-gnueabi setup the tests were already skipped
as unsupported so if you could test and confirm this fixes the 
issue you see would be great.

Thanks!

  Andrea


[-- Attachment #2: 0001-arm-testcase-Better-narrow-some-bfloat16-testcase.patch --]
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From d27e3f39fa2f348a4b8aa929bbb65808a09f1211 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Thu, 5 Nov 2020 08:57:03 +0000
Subject: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase

2020-11-05  Andrea Corallo  <andrea.corallo@arm.com>

	* gcc.target/arm/simd/vld1_lane_bf16_1.c: Add -mfloat-abi=hard
	flag.
	* gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
	* gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
	* gcc.target/arm/simd/vst1_lane_bf16_1.c: Likewise.
	* gcc.target/arm/simd/vst1_lane_bf16_indices_1.c: Likewise.
	* gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c: Likewise.
	* lib/target-supports.exp
	(check_effective_target_arm_v8_2a_bf16_neon_ok_nocache): Require
	target to support -mfloat-abi=hard.
---
 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c          | 2 +-
 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c  | 1 +
 gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c | 1 +
 gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c          | 2 +-
 gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c  | 1 +
 gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c | 1 +
 gcc/testsuite/lib/target-supports.exp                         | 4 ++++
 7 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
index fa4e45b7217..64e1f394676 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
@@ -1,7 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
-/* { dg-additional-options "-O3 --save-temps" } */
+/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
index c83eb53234d..9e56c25974e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
index 8e21e61c9c0..c75d24db11b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
index e018ec6592f..77e8a3bd5eb 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
@@ -1,7 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
-/* { dg-additional-options "-O3 --save-temps" } */
+/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
index 39870dc054c..ba4017afd0c 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c
index f31bd120fc2..4c96b491fb2 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 15f0649f8ae..2ab7e39756d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5213,6 +5213,10 @@ proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
         return 0;
     }
 
+    if { ! [check_effective_target_arm_hard_ok] } {
+	return 0;
+    }
+
     foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
         if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
             #include <arm_neon.h>
-- 
2.20.1

Re: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase

[Christophe Lyon]

On Thu, 5 Nov 2020 at 12:11, Andrea Corallo <andrea.corallo@arm.com> wrote:
>
> Christophe Lyon <christophe.lyon@linaro.org> writes:
>
> [...]
>
> >> I think you need to add -mfloat-abi=hard to the dg-additional-options
> >> otherwise vld1_lane_bf16_1.c
> >> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
> >>
> >> See bf16_vldn_1.c.
> >
> > Actually that's not sufficient because in turn we get:
> > /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
> > error: gnu/stubs-hard.h: No such file or directory
> >
> > So you should check that -mfloat-abi=hard is supported.
> >
> > Ditto for the vst tests.
>
> Hi Christophe,
>
> this patch should implement your suggestions.
>
> On my arm-none-linux-gnueabi setup the tests were already skipped
> as unsupported so if you could test and confirm this fixes the
> issue you see would be great.

Do you know why they are unsupported in your setup?

> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index 15f0649f8ae..2ab7e39756d 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -5213,6 +5213,10 @@ proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
>          return 0;
>      }
>
> +    if { ! [check_effective_target_arm_hard_ok] } {
> + return 0;
> +    }
> +
>     foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
>         if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
>             #include <arm_neon.h>

This seems strange since you would now exit early if
check_effective_target_arm_hard_ok is false, so you'll never need the
-mfloat-abi=softfp version of the flags.
BTW in general, I think softfp is tried before hard in the other
similar effective targets, any reason the order is different here?

Christophe

>
> Thanks!
>
>   Andrea
>

Re: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase

[Andrea Corallo]

Christophe Lyon <christophe.lyon@linaro.org> writes:

> On Thu, 5 Nov 2020 at 12:11, Andrea Corallo <andrea.corallo@arm.com> wrote:
>>
>> Christophe Lyon <christophe.lyon@linaro.org> writes:
>>
>> [...]
>>
>> >> I think you need to add -mfloat-abi=hard to the dg-additional-options
>> >> otherwise vld1_lane_bf16_1.c
>> >> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>> >>
>> >> See bf16_vldn_1.c.
>> >
>> > Actually that's not sufficient because in turn we get:
>> > /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
>> > error: gnu/stubs-hard.h: No such file or directory
>> >
>> > So you should check that -mfloat-abi=hard is supported.
>> >
>> > Ditto for the vst tests.
>>
>> Hi Christophe,
>>
>> this patch should implement your suggestions.
>>
>> On my arm-none-linux-gnueabi setup the tests were already skipped
>> as unsupported so if you could test and confirm this fixes the
>> issue you see would be great.
>
> Do you know why they are unsupported in your setup?

We probably have a different GCC configuration.  Could you share how
it's configured your?

>> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
>> index 15f0649f8ae..2ab7e39756d 100644
>> --- a/gcc/testsuite/lib/target-supports.exp
>> +++ b/gcc/testsuite/lib/target-supports.exp
>> @@ -5213,6 +5213,10 @@ proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
>>          return 0;
>>      }
>>
>> +    if { ! [check_effective_target_arm_hard_ok] } {
>> + return 0;
>> +    }
>> +
>>     foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
>>         if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
>>             #include <arm_neon.h>
>
> This seems strange since you would now exit early if
> check_effective_target_arm_hard_ok is false, so you'll never need the
> -mfloat-abi=softfp version of the flags.

So IIUC your suggestion would be to test with higher priority softfp and
in case we decide to go for hardfp make sure
check_effective_target_arm_hard_ok is satisfied.  Am I correct?

> BTW in general, I think softfp is tried before hard in the other
> similar effective targets, any reason the order is different here?

No idea.

Thanks

  Andrea

Re: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase

[Christophe Lyon]

On Thu, 5 Nov 2020 at 15:30, Andrea Corallo <andrea.corallo@arm.com> wrote:
>
> Christophe Lyon <christophe.lyon@linaro.org> writes:
>
> > On Thu, 5 Nov 2020 at 12:11, Andrea Corallo <andrea.corallo@arm.com> wrote:
> >>
> >> Christophe Lyon <christophe.lyon@linaro.org> writes:
> >>
> >> [...]
> >>
> >> >> I think you need to add -mfloat-abi=hard to the dg-additional-options
> >> >> otherwise vld1_lane_bf16_1.c
> >> >> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
> >> >>
> >> >> See bf16_vldn_1.c.
> >> >
> >> > Actually that's not sufficient because in turn we get:
> >> > /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
> >> > error: gnu/stubs-hard.h: No such file or directory
> >> >
> >> > So you should check that -mfloat-abi=hard is supported.
> >> >
> >> > Ditto for the vst tests.
> >>
> >> Hi Christophe,
> >>
> >> this patch should implement your suggestions.
> >>
> >> On my arm-none-linux-gnueabi setup the tests were already skipped
> >> as unsupported so if you could test and confirm this fixes the
> >> issue you see would be great.
> >
> > Do you know why they are unsupported in your setup?
>
> We probably have a different GCC configuration.  Could you share how
> it's configured your?
>
Sure, for instance:
--target=arm-none-linux-gnueabi --with-float=soft --with-mode=arm
--with-cpu=cortex-a9

> >> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> >> index 15f0649f8ae..2ab7e39756d 100644
> >> --- a/gcc/testsuite/lib/target-supports.exp
> >> +++ b/gcc/testsuite/lib/target-supports.exp
> >> @@ -5213,6 +5213,10 @@ proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
> >>          return 0;
> >>      }
> >>
> >> +    if { ! [check_effective_target_arm_hard_ok] } {
> >> + return 0;
> >> +    }
> >> +
> >>     foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
> >>         if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
> >>             #include <arm_neon.h>
> >
> > This seems strange since you would now exit early if
> > check_effective_target_arm_hard_ok is false, so you'll never need the
> > -mfloat-abi=softfp version of the flags.
>
> So IIUC your suggestion would be to test with higher priority softfp and
> in case we decide to go for hardfp make sure
> check_effective_target_arm_hard_ok is satisfied.  Am I correct?
>
ISTM that other tests that need hardfp check if it's supported in the
test, not in other effective targets.

For instance mve/intrinsics/mve_fpu1.c

I can see that quite a few tests that use -mfloat-abi=hard do not
check whether it's supported. Those I checked do not include
arm_neon.h and thus do not end up with the gnu/stubs-hard.h error
above.

> > BTW in general, I think softfp is tried before hard in the other
> > similar effective targets, any reason the order is different here?
>
> No idea.
>
> Thanks
>
>   Andrea

[PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

[Andrea Corallo]

[-- Attachment #1: Type: text/plain, Size: 3213 bytes --]

Christophe Lyon <christophe.lyon@linaro.org> writes:

> On Thu, 5 Nov 2020 at 15:30, Andrea Corallo <andrea.corallo@arm.com> wrote:
>>
>> Christophe Lyon <christophe.lyon@linaro.org> writes:
>>
>> > On Thu, 5 Nov 2020 at 12:11, Andrea Corallo <andrea.corallo@arm.com> wrote:
>> >>
>> >> Christophe Lyon <christophe.lyon@linaro.org> writes:
>> >>
>> >> [...]
>> >>
>> >> >> I think you need to add -mfloat-abi=hard to the dg-additional-options
>> >> >> otherwise vld1_lane_bf16_1.c
>> >> >> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>> >> >>
>> >> >> See bf16_vldn_1.c.
>> >> >
>> >> > Actually that's not sufficient because in turn we get:
>> >> > /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
>> >> > error: gnu/stubs-hard.h: No such file or directory
>> >> >
>> >> > So you should check that -mfloat-abi=hard is supported.
>> >> >
>> >> > Ditto for the vst tests.
>> >>
>> >> Hi Christophe,
>> >>
>> >> this patch should implement your suggestions.
>> >>
>> >> On my arm-none-linux-gnueabi setup the tests were already skipped
>> >> as unsupported so if you could test and confirm this fixes the
>> >> issue you see would be great.
>> >
>> > Do you know why they are unsupported in your setup?
>>
>> We probably have a different GCC configuration.  Could you share how
>> it's configured your?
>>
> Sure, for instance:
> --target=arm-none-linux-gnueabi --with-float=soft --with-mode=arm
> --with-cpu=cortex-a9

Thanks, I see now what was going on, my gas has no bf16 support so the
test was marked as unsupported.  Dunno why I assumed
check_no_compiler_messages_nocache wasn't testing the whole compilation
process.

>> >> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
>> >> index 15f0649f8ae..2ab7e39756d 100644
>> >> --- a/gcc/testsuite/lib/target-supports.exp
>> >> +++ b/gcc/testsuite/lib/target-supports.exp
>> >> @@ -5213,6 +5213,10 @@ proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
>> >>          return 0;
>> >>      }
>> >>
>> >> +    if { ! [check_effective_target_arm_hard_ok] } {
>> >> + return 0;
>> >> +    }
>> >> +
>> >>     foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
>> >>         if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
>> >>             #include <arm_neon.h>
>> >
>> > This seems strange since you would now exit early if
>> > check_effective_target_arm_hard_ok is false, so you'll never need the
>> > -mfloat-abi=softfp version of the flags.
>>
>> So IIUC your suggestion would be to test with higher priority softfp and
>> in case we decide to go for hardfp make sure
>> check_effective_target_arm_hard_ok is satisfied.  Am I correct?
>>
> ISTM that other tests that need hardfp check if it's supported in the
> test, not in other effective targets.
>
> For instance mve/intrinsics/mve_fpu1.c
>
> I can see that quite a few tests that use -mfloat-abi=hard do not
> check whether it's supported. Those I checked do not include
> arm_neon.h and thus do not end up with the gnu/stubs-hard.h error
> above.

I see thanks for the explaination.  The attached should do the job.

  Andrea


[-- Attachment #2: 0001-arm-testcase-Better-narrow-some-bfloat16-testcase.patch --]
[-- Type: text/plain, Size: 4785 bytes --]

From 1fc3854d1cb48840d7b8db9fcf7b2997a25f35f4 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Thu, 5 Nov 2020 08:57:03 +0000
Subject: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase

2020-11-05  Andrea Corallo  <andrea.corallo@arm.com>

	* gcc.target/arm/simd/vld1_lane_bf16_1.c: Require target to
	support and add -mfloat-abi=hard flag.
	* gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
	* gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
	* gcc.target/arm/simd/vst1_lane_bf16_1.c: Likewise.
	* gcc.target/arm/simd/vst1_lane_bf16_indices_1.c: Likewise.
	* gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c: Likewise.
---
 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c          | 3 ++-
 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c  | 2 ++
 gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c | 2 ++
 gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c          | 3 ++-
 gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c  | 2 ++
 gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c | 2 ++
 6 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
index fa4e45b7217..94fb38f32b8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
@@ -1,7 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
-/* { dg-additional-options "-O3 --save-temps" } */
+/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
index c83eb53234d..d9af512cf92 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
index 8e21e61c9c0..a73184c0f78 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
index e018ec6592f..8564b8fa062 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
@@ -1,7 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
-/* { dg-additional-options "-O3 --save-temps" } */
+/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
index 39870dc054c..1bd68718d10 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c b/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c
index f31bd120fc2..f18a4792a14 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
 
 #include "arm_neon.h"
 
-- 
2.20.1

Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

[Christophe Lyon]

On Fri, 6 Nov 2020 at 15:06, Andrea Corallo <andrea.corallo@arm.com> wrote:
>
> Christophe Lyon <christophe.lyon@linaro.org> writes:
>
> > On Thu, 5 Nov 2020 at 15:30, Andrea Corallo <andrea.corallo@arm.com> wrote:
> >>
> >> Christophe Lyon <christophe.lyon@linaro.org> writes:
> >>
> >> > On Thu, 5 Nov 2020 at 12:11, Andrea Corallo <andrea.corallo@arm.com> wrote:
> >> >>
> >> >> Christophe Lyon <christophe.lyon@linaro.org> writes:
> >> >>
> >> >> [...]
> >> >>
> >> >> >> I think you need to add -mfloat-abi=hard to the dg-additional-options
> >> >> >> otherwise vld1_lane_bf16_1.c
> >> >> >> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
> >> >> >>
> >> >> >> See bf16_vldn_1.c.
> >> >> >
> >> >> > Actually that's not sufficient because in turn we get:
> >> >> > /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
> >> >> > error: gnu/stubs-hard.h: No such file or directory
> >> >> >
> >> >> > So you should check that -mfloat-abi=hard is supported.
> >> >> >
> >> >> > Ditto for the vst tests.
> >> >>
> >> >> Hi Christophe,
> >> >>
> >> >> this patch should implement your suggestions.
> >> >>
> >> >> On my arm-none-linux-gnueabi setup the tests were already skipped
> >> >> as unsupported so if you could test and confirm this fixes the
> >> >> issue you see would be great.
> >> >
> >> > Do you know why they are unsupported in your setup?
> >>
> >> We probably have a different GCC configuration.  Could you share how
> >> it's configured your?
> >>
> > Sure, for instance:
> > --target=arm-none-linux-gnueabi --with-float=soft --with-mode=arm
> > --with-cpu=cortex-a9
>
> Thanks, I see now what was going on, my gas has no bf16 support so the
> test was marked as unsupported.  Dunno why I assumed
> check_no_compiler_messages_nocache wasn't testing the whole compilation
> process.
>
> >> >> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> >> >> index 15f0649f8ae..2ab7e39756d 100644
> >> >> --- a/gcc/testsuite/lib/target-supports.exp
> >> >> +++ b/gcc/testsuite/lib/target-supports.exp
> >> >> @@ -5213,6 +5213,10 @@ proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
> >> >>          return 0;
> >> >>      }
> >> >>
> >> >> +    if { ! [check_effective_target_arm_hard_ok] } {
> >> >> + return 0;
> >> >> +    }
> >> >> +
> >> >>     foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
> >> >>         if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
> >> >>             #include <arm_neon.h>
> >> >
> >> > This seems strange since you would now exit early if
> >> > check_effective_target_arm_hard_ok is false, so you'll never need the
> >> > -mfloat-abi=softfp version of the flags.
> >>
> >> So IIUC your suggestion would be to test with higher priority softfp and
> >> in case we decide to go for hardfp make sure
> >> check_effective_target_arm_hard_ok is satisfied.  Am I correct?
> >>
> > ISTM that other tests that need hardfp check if it's supported in the
> > test, not in other effective targets.
> >
> > For instance mve/intrinsics/mve_fpu1.c
> >
> > I can see that quite a few tests that use -mfloat-abi=hard do not
> > check whether it's supported. Those I checked do not include
> > arm_neon.h and thus do not end up with the gnu/stubs-hard.h error
> > above.
>
> I see thanks for the explaination.  The attached should do the job.
>

Yes, it works for me, thanks.

>   Andrea
>

Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

[Andrea Corallo]

Christophe Lyon <christophe.lyon@linaro.org> writes:
[...]
> Yes, it works for me, thanks.

Super, happy to push it when I get the okay.

  Andrea

RE: [PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

[Kyrylo Tkachov]

> -----Original Message-----
> From: Andrea Corallo <Andrea.Corallo@arm.com>
> Sent: 09 November 2020 10:05
> To: Christophe Lyon <christophe.lyon@linaro.org>
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org;
> Richard Earnshaw <Richard.Earnshaw@arm.com>; nd <nd@arm.com>
> Subject: Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16
> testcase
> 
> Christophe Lyon <christophe.lyon@linaro.org> writes:
> [...]
> > Yes, it works for me, thanks.
> 
> Super, happy to push it when I get the okay.

It's okay.
Thanks,
Kyrill

> 
>   Andrea

Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

[Andrea Corallo]

Kyrylo Tkachov <Kyrylo.Tkachov@arm.com> writes:

>> -----Original Message-----
>> From: Andrea Corallo <Andrea.Corallo@arm.com>
>> Sent: 09 November 2020 10:05
>> To: Christophe Lyon <christophe.lyon@linaro.org>
>> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org;
>> Richard Earnshaw <Richard.Earnshaw@arm.com>; nd <nd@arm.com>
>> Subject: Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16
>> testcase
>> 
>> Christophe Lyon <christophe.lyon@linaro.org> writes:
>> [...]
>> > Yes, it works for me, thanks.
>> 
>> Super, happy to push it when I get the okay.
>
> It's okay.
> Thanks,
> Kyrill

Installed into master as 2d4fa1f79c7.

Thanks

  Andrea