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Thu, 18 Jun 2020 09:43:27 +0000 Received: from DB7PR08MB3002.eurprd08.prod.outlook.com ([fe80::7953:31a2:720e:82d2]) by DB7PR08MB3002.eurprd08.prod.outlook.com ([fe80::7953:31a2:720e:82d2%4]) with mapi id 15.20.3109.021; Thu, 18 Jun 2020 09:43:27 +0000 From: Kyrylo Tkachov To: Srinath Parvathaneni , "gcc-patches@gcc.gnu.org" Subject: RE: [PATCH][GCC-10 Backport] arm: Fix MVE scalar shift intrinsics code-gen. Thread-Topic: [PATCH][GCC-10 Backport] arm: Fix MVE scalar shift intrinsics code-gen. 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X-Microsoft-Antispam-Message-Info: co5hui9LapMVIHffzHhrXqxL/6rAQXWYxrepYc4mqGT+hefbHd37wL4pTvarvELr20YBzemB5JCJnkMC/rg+mtzj77OZkAOMRyy13IxHc4F/ibUR/Q8g3JmDqthQYGQdPL/TTKN+fEMYTmfegwB/2ZQlkPXV4aNxI3VpTuvf+6FHronWphxGH6sMpK3r/vj+536yjo2ev2Y7LbsMxVpy6kT3UAeNlw9ksz/cVLjGoWJIWM1XgWi3eDCW9dMzuZ6xte+TGgFPT1pqtslATOVLEqgCAATORtaWhuOf5m3UkRVR6xex9DlQglXLHZLHOItx79cDF0IbKCDcDWVl0ueGdWEDkcy55bbreZmHX4SgF6aN4wKg4sK391JegGs0uHUbdNM651nbnVeIGuAtXThcfA== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2020 09:43:35.8174 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 906e18f3-3134-40b6-d7e2-08d8136c125a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR08MB2874 X-Spam-Status: No, score=-17.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_LOTSOFHASH, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Jun 2020 09:43:41 -0000 > -----Original Message----- > From: Srinath Parvathaneni > Sent: 17 June 2020 17:17 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov > Subject: [PATCH][GCC-10 Backport] arm: Fix MVE scalar shift intrinsics co= de- > gen. >=20 > Hello, >=20 > This patch modifies the MVE scalar shift RTL patterns. The current patter= ns > have wrong constraints and predicates due to which the values returned > from > MVE scalar shift instructions are overwritten in the code-gen. >=20 > example: > $ cat x.c > int32_t foo(int64_t acc, int shift) > { > return sqrshrl_sat48 (acc, shift); > } >=20 > Code-gen before applying this patch: > $ arm-none-eabi-gcc -march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard -O2 -S > $ cat x.s > foo: > push {r4, r5} > sqrshrl r0, r1, #48, r2 ----> (a) > mov r0, r4 ----> (b) > pop {r4, r5} > bx lr >=20 > Code-gen after applying this patch: > foo: > sqrshrl r0, r1, #48, r2 > bx lr >=20 > In the current compiler the return value (r0) from sqrshrl (a) is getting > overwritten by the mov statement (b). > This patch fixes above issue. >=20 > Regression tested on arm-none-eabi and found no regressions. >=20 > Ok for gcc-10 branch? >=20 Ok. Thanks, Kyrill > Thanks, > Srinath. >=20 > 2020-06-12 Srinath Parvathaneni >=20 > gcc/ > * config/arm/mve.md (mve_uqrshll_sat_di): Correct the > predicate > and constraint of all the operands. > (mve_sqrshrl_sat_di): Likewise. > (mve_uqrshl_si): Likewise. > (mve_sqrshr_si): Likewise. > (mve_uqshll_di): Likewise. > (mve_urshrl_di): Likewise. > (mve_uqshl_si): Likewise. > (mve_urshr_si): Likewise. > (mve_sqshl_si): Likewise. > (mve_srshr_si): Likewise. > (mve_srshrl_di): Likewise. > (mve_sqshll_di): Likewise. > * config/arm/predicates.md (arm_low_register_operand): Define. >=20 > gcc/testsuite/ > * gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c: New test. > * gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c: Likewise. > * gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c: Likewise. > * gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c: Likewise. >=20 > (cherry picked from commit 6af598703f919b56f628c496843cdfe6f0cb8276) >=20 >=20 > ############### Attachment also inlined for ease of reply > ############### >=20 >=20 > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index > 3a57901bd5bcd770832d59dc77cd92b6d9b5ecb4..9758862ac2bb40805dc5b6 > 6c9b05466fffcf91df 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -11344,9 +11344,9 @@ > ;; [uqrshll_di] > ;; > (define_insn "mve_uqrshll_sat_di" > - [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > - (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "s_register_operand" "r")] > + [(set (match_operand:DI 0 "arm_low_register_operand" "=3Dl") > + (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") > + (match_operand:SI 2 "register_operand" "r")] > UQRSHLLQ))] > "TARGET_HAVE_MVE" > "uqrshll%?\\t%Q1, %R1, #, %2" > @@ -11356,9 +11356,9 @@ > ;; [sqrshrl_di] > ;; > (define_insn "mve_sqrshrl_sat_di" > - [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > - (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "s_register_operand" "r")] > + [(set (match_operand:DI 0 "arm_low_register_operand" "=3Dl") > + (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") > + (match_operand:SI 2 "register_operand" "r")] > SQRSHRLQ))] > "TARGET_HAVE_MVE" > "sqrshrl%?\\t%Q1, %R1, #, %2" > @@ -11368,9 +11368,9 @@ > ;; [uqrshl_si] > ;; > (define_insn "mve_uqrshl_si" > - [(set (match_operand:SI 0 "arm_general_register_operand" "+r") > - (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "s_register_operand" "r")] > + [(set (match_operand:SI 0 "arm_general_register_operand" "=3Dr") > + (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" > "0") > + (match_operand:SI 2 "register_operand" "r")] > UQRSHL))] > "TARGET_HAVE_MVE" > "uqrshl%?\\t%1, %2" > @@ -11380,9 +11380,9 @@ > ;; [sqrshr_si] > ;; > (define_insn "mve_sqrshr_si" > - [(set (match_operand:SI 0 "arm_general_register_operand" "+r") > - (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "s_register_operand" "r")] > + [(set (match_operand:SI 0 "arm_general_register_operand" "=3Dr") > + (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" > "0") > + (match_operand:SI 2 "register_operand" "r")] > SQRSHR))] > "TARGET_HAVE_MVE" > "sqrshr%?\\t%1, %2" > @@ -11392,9 +11392,9 @@ > ;; [uqshll_di] > ;; > (define_insn "mve_uqshll_di" > - [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > - (us_ashift:DI (match_operand:DI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "arm_reg_or_long_shift_imm" > "rPg")))] > + [(set (match_operand:DI 0 "arm_low_register_operand" "=3Dl") > + (us_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0") > + (match_operand:SI 2 "immediate_operand" "Pg")))] > "TARGET_HAVE_MVE" > "uqshll%?\\t%Q1, %R1, %2" > [(set_attr "predicable" "yes")]) > @@ -11403,9 +11403,9 @@ > ;; [urshrl_di] > ;; > (define_insn "mve_urshrl_di" > - [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > - (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")] > + [(set (match_operand:DI 0 "arm_low_register_operand" "=3Dl") > + (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") > + (match_operand:SI 2 "immediate_operand" "Pg")] > URSHRL))] > "TARGET_HAVE_MVE" > "urshrl%?\\t%Q1, %R1, %2" > @@ -11415,9 +11415,9 @@ > ;; [uqshl_si] > ;; > (define_insn "mve_uqshl_si" > - [(set (match_operand:SI 0 "arm_general_register_operand" "+r") > - (us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "arm_reg_or_long_shift_imm" > "rPg")))] > + [(set (match_operand:SI 0 "arm_general_register_operand" "=3Dr") > + (us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" > "0") > + (match_operand:SI 2 "immediate_operand" "Pg")))] > "TARGET_HAVE_MVE" > "uqshl%?\\t%1, %2" > [(set_attr "predicable" "yes")]) > @@ -11426,9 +11426,9 @@ > ;; [urshr_si] > ;; > (define_insn "mve_urshr_si" > - [(set (match_operand:SI 0 "arm_general_register_operand" "+r") > - (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")] > + [(set (match_operand:SI 0 "arm_general_register_operand" "=3Dr") > + (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" > "0") > + (match_operand:SI 2 "immediate_operand" "Pg")] > URSHR))] > "TARGET_HAVE_MVE" > "urshr%?\\t%1, %2" > @@ -11438,9 +11438,9 @@ > ;; [sqshl_si] > ;; > (define_insn "mve_sqshl_si" > - [(set (match_operand:SI 0 "arm_general_register_operand" "+r") > - (ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "arm_reg_or_long_shift_imm" > "rPg")))] > + [(set (match_operand:SI 0 "arm_general_register_operand" "=3Dr") > + (ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" > "0") > + (match_operand:SI 2 "immediate_operand" "Pg")))] > "TARGET_HAVE_MVE" > "sqshl%?\\t%1, %2" > [(set_attr "predicable" "yes")]) > @@ -11449,9 +11449,9 @@ > ;; [srshr_si] > ;; > (define_insn "mve_srshr_si" > - [(set (match_operand:SI 0 "arm_general_register_operand" "+r") > - (unspec:SI [(match_operand:DI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")] > + [(set (match_operand:SI 0 "arm_general_register_operand" "=3Dr") > + (unspec:SI [(match_operand:DI 1 "arm_general_register_operand" > "0") > + (match_operand:SI 2 "immediate_operand" "Pg")] > SRSHR))] > "TARGET_HAVE_MVE" > "srshr%?\\t%1, %2" > @@ -11461,9 +11461,9 @@ > ;; [srshrl_di] > ;; > (define_insn "mve_srshrl_di" > - [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > - (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")] > + [(set (match_operand:DI 0 "arm_low_register_operand" "=3Dl") > + (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") > + (match_operand:SI 2 "immediate_operand" "Pg")] > SRSHRL))] > "TARGET_HAVE_MVE" > "srshrl%?\\t%Q1, %R1, %2" > @@ -11473,9 +11473,9 @@ > ;; [sqshll_di] > ;; > (define_insn "mve_sqshll_di" > - [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > - (ss_ashift:DI (match_operand:DI 1 "arm_general_register_operand" > "r") > - (match_operand:SI 2 "arm_reg_or_long_shift_imm" > "rPg")))] > + [(set (match_operand:DI 0 "arm_low_register_operand" "=3Dl") > + (ss_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0") > + (match_operand:SI 2 "immediate_operand" "Pg")))] > "TARGET_HAVE_MVE" > "sqshll%?\\t%Q1, %R1, %2" > [(set_attr "predicable" "yes")]) > diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md > index > 9e9bca4d87fdc31e045b2b5bb03b996f082079bd..371b43cd86115565f8abf2e > 91383f7012b87f390 100644 > --- a/gcc/config/arm/predicates.md > +++ b/gcc/config/arm/predicates.md > @@ -155,6 +155,18 @@ > || REGNO (op) >=3D FIRST_PSEUDO_REGISTER)); > }) >=20 > +;; Low core register, or any pseudo. > +(define_predicate "arm_low_register_operand" > + (match_code "reg,subreg") > +{ > + if (GET_CODE (op) =3D=3D SUBREG) > + op =3D SUBREG_REG (op); > + > + return (REG_P (op) > + && (REGNO (op) <=3D LAST_LO_REGNUM > + || REGNO (op) >=3D FIRST_PSEUDO_REGISTER)); > +}) > + > (define_predicate "arm_general_adddi_operand" > (ior (match_operand 0 "arm_general_register_operand") > (and (match_code "const_int") > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shift= s1.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..e1c136e7f302c1824f0b00b > 5e7bc468ff5fcfe27 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c > @@ -0,0 +1,40 @@ > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ > +/* { dg-options "-O2" } */ > +/* { dg-add-options arm_v8_1m_mve } */ > + > +#include "arm_mve.h" > +#include "stdio.h" > +#include > + > +void > +foo (int64_t acc, int shift) > +{ > + acc =3D sqrshrl_sat48 (acc, shift); > + if (acc !=3D 16) > + abort(); > + acc =3D sqrshrl (acc, shift); > + if (acc !=3D 2) > + abort(); > +} > + > +void > +foo1 (uint64_t acc, int shift) > +{ > + acc =3D uqrshll_sat48 (acc, shift); > + if (acc !=3D 16) > + abort(); > + acc =3D uqrshll (acc, shift); > + if (acc !=3D 128) > + abort(); > +} > + > +int main() > +{ > + int64_t acc =3D 128; > + uint64_t acc1 =3D 2; > + int shift =3D 3; > + foo (acc, shift); > + foo1 (acc1, shift); > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shift= s2.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..0b5a8edb15849913d4f2849 > ab86decb286692386 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c > @@ -0,0 +1,35 @@ > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ > +/* { dg-options "-O2" } */ > +/* { dg-add-options arm_v8_1m_mve } */ > + > +#include "arm_mve.h" > +#include "stdio.h" > +#include > + > +#define IMM 3 > + > +void > +foo (int64_t acc, uint64_t acc1) > +{ > + acc =3D sqshll (acc, IMM); > + if (acc !=3D 128) > + abort(); > + acc =3D srshrl (acc, IMM); > + if (acc !=3D 16) > + abort(); > + acc1 =3D uqshll (acc1, IMM); > + if (acc1 !=3D 128) > + abort(); > + acc1 =3D urshrl (acc1, IMM); > + if (acc1 !=3D 16) > + abort(); > +} > + > +int main() > +{ > + int64_t acc =3D 16; > + uint64_t acc1 =3D 16; > + foo (acc, acc1); > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shift= s3.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..7e3da54f5e62467e2cdaabd > 85df3db127f608802 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c > @@ -0,0 +1,28 @@ > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ > +/* { dg-options "-O2" } */ > +/* { dg-add-options arm_v8_1m_mve } */ > + > +#include "arm_mve.h" > +#include "stdio.h" > +#include > + > +void > +foo (int32_t acc, uint32_t acc1, int shift) > +{ > + acc =3D sqrshr (acc, shift); > + if (acc !=3D 16) > + abort(); > + acc1 =3D uqrshl (acc1, shift); > + if (acc1 !=3D 128) > + abort(); > +} > + > +int main() > +{ > + int32_t acc =3D 128; > + uint32_t acc1 =3D 16; > + int shift =3D 3; > + foo (acc, acc1, shift); > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shift= s4.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..8bee12f7fdfaef51daf7e2f5 > d3c1e284115d2649 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c > @@ -0,0 +1,34 @@ > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ > +/* { dg-options "-O2" } */ > +/* { dg-add-options arm_v8_1m_mve } */ > + > +#include "arm_mve.h" > +#include > + > +#define IMM 3 > + > +void > +foo (int32_t acc, uint32_t acc1) > +{ > + acc =3D sqshl (acc, IMM); > + if (acc !=3D 128) > + abort(); > + acc =3D srshr (acc, IMM); > + if (acc !=3D 16) > + abort(); > + acc1 =3D uqshl (acc1, IMM); > + if (acc1 !=3D 128) > + abort(); > + acc1 =3D urshr (acc1, IMM); > + if (acc1 !=3D 16) > + abort(); > +} > + > +int main() > +{ > + int32_t acc =3D 16; > + uint32_t acc1 =3D 16; > + foo (acc, acc1); > + return 0; > +}