[wwwdocs] Move arm section under aarch64

[wwwdocs] Move arm section under aarch64

[Kyrylo Tkachov]

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Hi all,

We logically grouped the aarch64 and arm entries as they share some content but
then the alphabetic order came in and put amdgcn and arc between the two.
I'm taking the liberty of moving arm under aarch64 and adding a small clarification
that the recently added CDE intrinsics implement a beta version of the ACLE specification.

Pushing to wwwdocs.

Thanks,
Kyrill

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diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index 389561d1..c24d1f84 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -567,26 +567,6 @@ a work-in-progress.</p>
   </li>
 </ul>
 
-<h3 id="amdgcn">AMD Radeon (GCN)</h3>
-<ul>
-  <li>The code generation and in particular the vectorization support has been
-  much improved.</li>
-</ul>
-
-<h3 id="arc">ARC</h3>
-<ul>
-  <li>The interrupt service routine functions save all used
-  registers, including extension registers and auxiliary registers
-  used by Zero Overhead Loops.</li>
-  <li>Improve code size by using multiple short instructions instead of
-  a single long <code>mov</code> or <code>ior</code> instruction when its
-  long immediate constant is known.</li>
-  <li>Fix usage of the accumulator register for ARC600.</li>
-  <li>Fix issues with <code>uncached</code> attribute.</li>
-  <li>Remove <code>-mq-class</code> option.</li>
-  <li>Improve 64-bit integer addition and subtraction operations.</li>
-</ul>
-
 <h3 id="arm">arm</h3>
 <ul>
   <li>Support for the FDPIC ABI has been added. It uses 64-bit
@@ -606,8 +586,8 @@ a work-in-progress.</p>
        (GCC identifiers in parentheses):
        <ul>
          <li>Arm Cortex-A77 (<code>cortex-a77</code>).</li>
-	 <li>Arm Cortex-A76AE (<code>cortex-a76ae</code>).</li>
-	 <li>Arm Cortex-M35P (<code>cortex-m35p</code>).</li>
+         <li>Arm Cortex-A76AE (<code>cortex-a76ae</code>).</li>
+         <li>Arm Cortex-M35P (<code>cortex-m35p</code>).</li>
        </ul>
        The GCC identifiers can be used
        as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
@@ -624,11 +604,32 @@ a work-in-progress.</p>
   added: this M-profile feature is no longer restricted to targets
   with <code>MOVT</code>. For example, <code>-mcpu=cortex-m0</code>
   now supports this option.</li>
-  <li>Support for the Custom Datapath Extension ACLE
+  <li>Support for the Custom Datapath Extension beta ACLE
   <a href="https://developer.arm.com/docs/101028/0010/custom-datapath-extension">
   intrinsics</a> has been added.</li>
 </ul>
 
+
+<h3 id="amdgcn">AMD Radeon (GCN)</h3>
+<ul>
+  <li>The code generation and in particular the vectorization support has been
+  much improved.</li>
+</ul>
+
+<h3 id="arc">ARC</h3>
+<ul>
+  <li>The interrupt service routine functions save all used
+  registers, including extension registers and auxiliary registers
+  used by Zero Overhead Loops.</li>
+  <li>Improve code size by using multiple short instructions instead of
+  a single long <code>mov</code> or <code>ior</code> instruction when its
+  long immediate constant is known.</li>
+  <li>Fix usage of the accumulator register for ARC600.</li>
+  <li>Fix issues with <code>uncached</code> attribute.</li>
+  <li>Remove <code>-mq-class</code> option.</li>
+  <li>Improve 64-bit integer addition and subtraction operations.</li>
+</ul>
+
 <h3 id="avr">AVR</h3>
 <ul>
   <li>Support for the XMEGA-like devices