From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80073.outbound.protection.outlook.com [40.107.8.73]) by sourceware.org (Postfix) with ESMTPS id 4BD73385F02A for ; Thu, 2 Apr 2020 09:58:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 4BD73385F02A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=Kyrylo.Tkachov@arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=q7jRT29peQkwaeHQs4ItBUmV+BjZ5CB4wHxktTtXwDA=; b=lvjV8EwDnMffAtdKiQ+/sIpHIT+Qs04TLCsqPI47+RJbbEaPoUKyYIgJ3fpCw1bebrqeIar115Fj06ch/EcoEHWhMJvK7kZRJF6KWc3EkeDbtBRfg8SgsjF08V+zq2zrwsW56sjKlpuGn6uA4cizxLkbxXMaqz8MLGzpjJIlBTY= Received: from DB7PR02CA0032.eurprd02.prod.outlook.com (2603:10a6:10:52::45) by DB6PR08MB2824.eurprd08.prod.outlook.com (2603:10a6:6:23::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2856.19; Thu, 2 Apr 2020 09:58:19 +0000 Received: from DB5EUR03FT034.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:52:cafe::4d) by DB7PR02CA0032.outlook.office365.com (2603:10a6:10:52::45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2878.15 via Frontend Transport; Thu, 2 Apr 2020 09:58:19 +0000 Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; gcc.gnu.org; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;gcc.gnu.org; dmarc=bestguesspass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DB5EUR03FT034.mail.protection.outlook.com (10.152.20.87) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2856.17 via Frontend Transport; Thu, 2 Apr 2020 09:58:19 +0000 Received: ("Tessian outbound e2c88df8bbbe:v50"); Thu, 02 Apr 2020 09:58:19 +0000 X-CR-MTA-TID: 64aa7808 Received: from de6f84a00721.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 1F2C1BC5-275A-46FB-AE90-33ECA13C9095.1; Thu, 02 Apr 2020 09:58:14 +0000 Received: from EUR02-AM5-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id de6f84a00721.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 02 Apr 2020 09:58:14 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EwtMOHbyGuyNxkVejq0micVQMKvxurmHh0/bJZomijsnowtzLc2TQHSRfH+jVEPGzEqumVejeeKsNPEwVuEiMjhsr3zmX9mfcmncaDUZjGrJ7gdUAiNI3EYEXu/KizST4+IOPWsQ7qQjHfvYpUfW+QO1PnKH0RmhBP2nEFTMJ81MlUmagP0wsIdpf9pkOTAFvGdv8vXHvCEJjYsGFtoFMJCvI7odLUTmzu1pVmJolOhSB7EwAUNHr+XrDgFk8yR2oBg+XzbDZ5qOEcE6PftCsO/c8HPsU7fOMPyAU9jzko9JbhIOd+dyEcBn5JIGinE9IGAj6xfjishARf03ehjRNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=q7jRT29peQkwaeHQs4ItBUmV+BjZ5CB4wHxktTtXwDA=; b=aC48TZH6eZVl1uXfjcKV1LMy5vQR8ToHhxQqRHbEmrshT9l/YBO3oafcHkfqhl+ygUIpx5L1dtv4aTeXgP2R+Z3m5Xk0w2ysugVOJJ0PqqMaMFD1T7rSzi0JeJ8WOWyzlbz3ZGSoH+sj3wC+Np5tATDnMx8wZ9Sk9SWiGXHo6iJ5tCTz7ZX3N3BMPactGMH4lu8ft0xrOzI03w9fA4+WStMd9Iv7w2Gz8ruRrv5z/nspztPJRypUXZUmKFwXRQdle/dT9K1qlaw7QlPBGUxolZAgrG7TgtcXI3NyCdfAMRrKZ2ftJmzDFrHsh7jD6yv0rTATiP6bxQ+ekNHMBkR5zA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=q7jRT29peQkwaeHQs4ItBUmV+BjZ5CB4wHxktTtXwDA=; b=lvjV8EwDnMffAtdKiQ+/sIpHIT+Qs04TLCsqPI47+RJbbEaPoUKyYIgJ3fpCw1bebrqeIar115Fj06ch/EcoEHWhMJvK7kZRJF6KWc3EkeDbtBRfg8SgsjF08V+zq2zrwsW56sjKlpuGn6uA4cizxLkbxXMaqz8MLGzpjJIlBTY= Received: from DB7PR08MB3002.eurprd08.prod.outlook.com (52.134.111.153) by DB7PR08MB3100.eurprd08.prod.outlook.com (52.135.131.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2856.20; Thu, 2 Apr 2020 09:58:12 +0000 Received: from DB7PR08MB3002.eurprd08.prod.outlook.com ([fe80::2c3f:e5d1:183f:4731]) by DB7PR08MB3002.eurprd08.prod.outlook.com ([fe80::2c3f:e5d1:183f:4731%7]) with mapi id 15.20.2856.019; Thu, 2 Apr 2020 09:58:12 +0000 From: Kyrylo Tkachov To: Srinath Parvathaneni , "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw Subject: RE: [GCC][PATCH][ARM]: Fix for MVE ACLE intrinsics with writeback (PR94317). Thread-Topic: [GCC][PATCH][ARM]: Fix for MVE ACLE intrinsics with writeback (PR94317). Thread-Index: AQHWB3eCLMZVoTDG+kCYZFJX0ORCj6hlm20Q Date: Thu, 2 Apr 2020 09:58:12 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: 1dce7d8b-8f21-4896-bc8e-184d8ef1a019.0 x-checkrecipientchecked: true Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Kyrylo.Tkachov@arm.com; x-originating-ip: [80.5.218.175] x-ms-publictraffictype: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 015534fa-4d05-4e01-a51b-08d7d6ec5f20 x-ms-traffictypediagnostic: DB7PR08MB3100:|DB7PR08MB3100:|DB6PR08MB2824: x-ms-exchange-transport-forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true nodisclaimer: true x-ms-oob-tlc-oobclassifiers: OLM:454;OLM:454; x-forefront-prvs: 0361212EA8 X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DB7PR08MB3002.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(10009020)(4636009)(376002)(136003)(396003)(39860400002)(366004)(346002)(71200400001)(966005)(5660300002)(7696005)(53546011)(186003)(2906002)(33656002)(76116006)(26005)(30864003)(110136005)(66476007)(55016002)(66946007)(6506007)(52536014)(8676002)(81156014)(81166006)(66446008)(86362001)(8936002)(66556008)(4326008)(64756008)(478600001)(9686003)(316002)(579004)(559001); DIR:OUT; SFP:1101; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: saNV7QQ17ttyAIleupmsKzMyiQsN9pSAG0WhemBa3kxlEu6n4HUPauLnawWniM/mwXYmM9fkYXcBXjZHCz6DncKoo8DujHAKidGsVsnhSJ2WJK1ScYIIPwZvgsAU3QlDUOr0rAhUlZ75WrbUy7kg0qz98nyzvom/zf4cG6w9r0yYL1YRbSusH/7U+ZQdUTdXqINznX8/zjNzbVjPiMMrrAkgGt6sf+IA5PqtlOhj3ySPEc4cINj7NEvXY5MN7PTMUAGVdD2j/52pCWDM2PQQleGIQ5BbrByGZgmbn8UG/HllhyNiClIwaBeqgRzB4i7s6ZKxmECRCw53t776/MZXUIcHipi24l1Ow/Q2VA2XDFVtL/m06nuY2DjV26AxQ6e8HmSvOKc715sY5MbsIV13vCbRbEIwnQiSrzgePpPdAOdbyDfMJXDdfg8PlFbdG4wM/+9URWLqO8xTxW5eV1XwUlteiy0y/9NSVTissxs0CmTwyX+DPui+iCGX6zZw9IPAd72rrFj1hOcu2DOIfgOCmA== x-ms-exchange-antispam-messagedata: bejQ/ASEqyWTwhA1XQlQovFlpsB5IagnSCMZ+4AypUbuFY1dmb+N/e6z8aMufbXMznrp77H4cb3/icmaXH6N56XAVbSH1Ef9SGLR0tV+ftaYV7pewzVUCAVCYFCKh+X9NuFd1rDsKhem8w684AFu1g== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3100 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Kyrylo.Tkachov@arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5EUR03FT034.eop-EUR03.prod.protection.outlook.com X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFTY:; SFS:(10009020)(4636009)(396003)(39860400002)(376002)(346002)(136003)(46966005)(81166006)(8676002)(26005)(26826003)(7696005)(966005)(81156014)(2906002)(186003)(70206006)(8936002)(478600001)(70586007)(86362001)(6506007)(316002)(336012)(9686003)(52536014)(30864003)(356004)(47076004)(5660300002)(82740400003)(33656002)(55016002)(110136005)(4326008)(53546011); DIR:OUT; SFP:1101; X-MS-Office365-Filtering-Correlation-Id-Prvs: 2369669e-dc4c-4ef2-8b82-08d7d6ec5b21 X-Forefront-PRVS: 0361212EA8 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CxQ6iNvIvXqklTXqMtvmApf4gtQlWThaXw8eTt1Zo5WpCVm5JjTu/Iw2wxrOvqdTt6jRaOcFUcUo7pYYuFevgU7xdHxakQMfFI4Iq9woZGrO4mzuko/nqg7H7EvTl6+FX3jTKYEPSX2d0PI53U5IVOP1rbB8uGIS2Kn87qRHa4f4I57WdTSIMd9kV5fsKZbgMJ6MtZR1oCxo54Oo5UTNC8+1cwKES8GxLwmYsQ90tq5lAqMQx6dsj+/d5KyK5f/Y4si6P9ZhPjgnZ72KW5L+871PwJnxPhG/EyaUAqGqtVR+8tLbytZ7t3udTUKDJScSLjQDNFzcde7t/iFpb1FbMkZOKsIXygoP2B64IsQeJ9HZBXvNODA13aVmNzE2aNM6fpDccfo8R8rwH3hQ1mgufipVeuBZ1IrvZ3+qc7GMPKX/fHfG/Jhsp54y8FO32Pl9s9l2FVvxVA8jknN+OdFBHME2Yb51tMJezPIAwqt+5MAZhbWdYhj7Yv+E0WTaXCNBebIkrtqtvUj173ImDd9iTxtpaiaTP+oZbJ0cS2kujnfTNmkwZwPzePB96rUidC0cbDhIZC1xmWVOkD2bHhHuVosebOrvi7GagD4XDRzDivI= X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2020 09:58:19.2735 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 015534fa-4d05-4e01-a51b-08d7d6ec5f20 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR08MB2824 X-Spam-Status: No, score=-31.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Apr 2020 09:58:26 -0000 Hi Srinath, > -----Original Message----- > From: Srinath Parvathaneni > Sent: 31 March 2020 17:13 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > > Subject: [GCC][PATCH][ARM]: Fix for MVE ACLE intrinsics with writeback > (PR94317). >=20 > Hello, >=20 > Following MVE ACLE intrinsics have an issue with writeback to the base > address. >=20 > vldrdq_gather_base_wb_s64, vldrdq_gather_base_wb_u64, > vldrdq_gather_base_wb_z_s64, vldrdq_gather_base_wb_z_u64, > vldrwq_gather_base_wb_s32, vldrwq_gather_base_wb_u32, > vldrwq_gather_base_wb_z_s32, vldrwq_gather_base_wb_z_u32, > vldrwq_gather_base_wb_f32, vldrwq_gather_base_wb_z_f32. >=20 > This patch fixes the bug reported in PR94317 by adding separate builtin c= alls > to update the result and writeback to base address for the above intrinsi= cs. >=20 > Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more > details. > [1] https://developer.arm.com/architectures/instruction-sets/simd- > isas/helium/mve-intrinsics >=20 > Regression tested on arm-none-eabi and found no regressions. >=20 > Ok for trunk? Thanks, I've pushed this patch to master. Kyrill >=20 > Thanks, > Srinath. >=20 > gcc/ChangeLog: >=20 > 2020-03-31 Srinath Parvathaneni >=20 > PR target/94317 > * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define. > (LDRGBWBXU_Z_QUALIFIERS): Likewise. > * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): > Modify > intrinsic defintion by adding a new builtin call to writeback into base > address. > (__arm_vldrdq_gather_base_wb_u64): Likewise. > (__arm_vldrdq_gather_base_wb_z_s64): Likewise. > (__arm_vldrdq_gather_base_wb_z_u64): Likewise. > (__arm_vldrwq_gather_base_wb_s32): Likewise. > (__arm_vldrwq_gather_base_wb_u32): Likewise. > (__arm_vldrwq_gather_base_wb_z_s32): Likewise. > (__arm_vldrwq_gather_base_wb_z_u32): Likewise. > (__arm_vldrwq_gather_base_wb_f32): Likewise. > (__arm_vldrwq_gather_base_wb_z_f32): Likewise. > * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): > Modify > builtin's qualifier. > (vldrdq_gather_base_wb_z_u): Likewise. > (vldrwq_gather_base_wb_u): Likewise. > (vldrdq_gather_base_wb_u): Likewise. > (vldrwq_gather_base_wb_z_s): Likewise. > (vldrwq_gather_base_wb_z_f): Likewise. > (vldrdq_gather_base_wb_z_s): Likewise. > (vldrwq_gather_base_wb_s): Likewise. > (vldrwq_gather_base_wb_f): Likewise. > (vldrdq_gather_base_wb_s): Likewise. > (vldrwq_gather_base_nowb_z_u): Define builtin. > (vldrdq_gather_base_nowb_z_u): Likewise. > (vldrwq_gather_base_nowb_u): Likewise. > (vldrdq_gather_base_nowb_u): Likewise. > (vldrwq_gather_base_nowb_z_s): Likewise. > (vldrwq_gather_base_nowb_z_f): Likewise. > (vldrdq_gather_base_nowb_z_s): Likewise. > (vldrwq_gather_base_nowb_s): Likewise. > (vldrwq_gather_base_nowb_f): Likewise. > (vldrdq_gather_base_nowb_s): Likewise. > * config/arm/mve.md (mve_vldrwq_gather_base_nowb_v4si): > Define RTL > pattern. > (mve_vldrwq_gather_base_wb_v4si): Modify RTL pattern. > (mve_vldrwq_gather_base_nowb_z_v4si): Define RTL pattern. > (mve_vldrwq_gather_base_wb_z_v4si): Modify RTL pattern. > (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern. > (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern. > (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern. > (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern. > (mve_vldrdq_gather_base_nowb_v4di): Define RTL pattern. > (mve_vldrdq_gather_base_wb_v4di): Modify RTL pattern. > (mve_vldrdq_gather_base_nowb_z_v4di): Define RTL pattern. > (mve_vldrdq_gather_base_wb_z_v4di): Modify RTL pattern. >=20 > gcc/testsuite/ChangeLog: >=20 > 2020-03-31 Srinath Parvathaneni >=20 > PR target/94317 > * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: > Modify > * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: > Likewise. >=20 >=20 >=20 > ############### Attachment also inlined for ease of reply > ############### >=20 >=20 > diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.= c > index > 56f0db21ea95dcd738877daba27f1cb60f0d5a32..832b9107424fd9a4a0ee272 > b773b3d0929172370 100644 > --- a/gcc/config/arm/arm-builtins.c > +++ b/gcc/config/arm/arm-builtins.c > @@ -719,6 +719,17 @@ > arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers[SIMD_M > AX_BUILTIN_ARGS] > (arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers) >=20 > static enum arm_type_qualifiers > +arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + =3D { qualifier_unsigned, qualifier_unsigned, qualifier_immediate}; > +#define LDRGBWBXU_QUALIFIERS (arm_ldrgbwbxu_qualifiers) > + > +static enum arm_type_qualifiers > +arm_ldrgbwbxu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + =3D { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, > + qualifier_unsigned}; > +#define LDRGBWBXU_Z_QUALIFIERS (arm_ldrgbwbxu_z_qualifiers) > + > +static enum arm_type_qualifiers > arm_ldrgbwbs_qualifiers[SIMD_MAX_BUILTIN_ARGS] > =3D { qualifier_none, qualifier_unsigned, qualifier_immediate}; #defi= ne > LDRGBWBS_QUALIFIERS (arm_ldrgbwbs_qualifiers) diff --git > a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index > f1dcdc2153217e796c58526ba0e5be11be642234..47a6268e0800958f49d4623 > 8fe34ec749d243929 100644 > --- a/gcc/config/arm/arm_mve.h > +++ b/gcc/config/arm/arm_mve.h > @@ -13903,8 +13903,8 @@ __attribute__ ((__always_inline__, > __gnu_inline__, __artificial__)) > __arm_vldrdq_gather_base_wb_s64 (uint64x2_t * __addr, const int __offset= ) > { > int64x2_t > - result =3D __builtin_mve_vldrdq_gather_base_wb_sv2di (*__addr, __offse= t); > - __addr +=3D __offset; > + result =3D __builtin_mve_vldrdq_gather_base_nowb_sv2di (*__addr, > + __offset); *__addr =3D __builtin_mve_vldrdq_gather_base_wb_sv2di > + (*__addr, __offset); > return result; > } >=20 > @@ -13913,8 +13913,8 @@ __attribute__ ((__always_inline__, > __gnu_inline__, __artificial__)) > __arm_vldrdq_gather_base_wb_u64 (uint64x2_t * __addr, const int > __offset) { > uint64x2_t > - result =3D __builtin_mve_vldrdq_gather_base_wb_uv2di (*__addr, __offse= t); > - __addr +=3D __offset; > + result =3D __builtin_mve_vldrdq_gather_base_nowb_uv2di (*__addr, > + __offset); *__addr =3D __builtin_mve_vldrdq_gather_base_wb_uv2di > + (*__addr, __offset); > return result; > } >=20 > @@ -13923,8 +13923,8 @@ __attribute__ ((__always_inline__, > __gnu_inline__, __artificial__)) > __arm_vldrdq_gather_base_wb_z_s64 (uint64x2_t * __addr, const int > __offset, mve_pred16_t __p) { > int64x2_t > - result =3D __builtin_mve_vldrdq_gather_base_wb_z_sv2di (*__addr, __off= set, > __p); > - __addr +=3D __offset; > + result =3D __builtin_mve_vldrdq_gather_base_nowb_z_sv2di (*__addr, > + __offset, __p); *__addr =3D __builtin_mve_vldrdq_gather_base_wb_z_sv2d= i > + (*__addr, __offset, __p); > return result; > } >=20 > @@ -13933,8 +13933,8 @@ __attribute__ ((__always_inline__, > __gnu_inline__, __artificial__)) > __arm_vldrdq_gather_base_wb_z_u64 (uint64x2_t * __addr, const int > __offset, mve_pred16_t __p) { > uint64x2_t > - result =3D __builtin_mve_vldrdq_gather_base_wb_z_uv2di (*__addr, > __offset, __p); > - __addr +=3D __offset; > + result =3D __builtin_mve_vldrdq_gather_base_nowb_z_uv2di (*__addr, > + __offset, __p); *__addr =3D __builtin_mve_vldrdq_gather_base_wb_z_uv2d= i > + (*__addr, __offset, __p); > return result; > } >=20 > @@ -13943,8 +13943,8 @@ __attribute__ ((__always_inline__, > __gnu_inline__, __artificial__)) > __arm_vldrwq_gather_base_wb_s32 (uint32x4_t * __addr, const int > __offset) { > int32x4_t > - result =3D __builtin_mve_vldrwq_gather_base_wb_sv4si (*__addr, __offse= t); > - __addr +=3D __offset; > + result =3D __builtin_mve_vldrwq_gather_base_nowb_sv4si (*__addr, > + __offset); *__addr =3D __builtin_mve_vldrwq_gather_base_wb_sv4si > + (*__addr, __offset); > return result; > } >=20 > @@ -13953,8 +13953,8 @@ __attribute__ ((__always_inline__, > __gnu_inline__, __artificial__)) > __arm_vldrwq_gather_base_wb_u32 (uint32x4_t * __addr, const int > __offset) { > uint32x4_t > - result =3D __builtin_mve_vldrwq_gather_base_wb_uv4si (*__addr, __offse= t); > - __addr +=3D __offset; > + result =3D __builtin_mve_vldrwq_gather_base_nowb_uv4si (*__addr, > + __offset); *__addr =3D __builtin_mve_vldrwq_gather_base_wb_uv4si > + (*__addr, __offset); > return result; > } >=20 > @@ -13963,8 +13963,8 @@ __attribute__ ((__always_inline__, > __gnu_inline__, __artificial__)) > __arm_vldrwq_gather_base_wb_z_s32 (uint32x4_t * __addr, const int > __offset, mve_pred16_t __p) { > int32x4_t > - result =3D __builtin_mve_vldrwq_gather_base_wb_z_sv4si (*__addr, > __offset, __p); > - __addr +=3D __offset; > + result =3D __builtin_mve_vldrwq_gather_base_nowb_z_sv4si (*__addr, > + __offset, __p); *__addr =3D __builtin_mve_vldrwq_gather_base_wb_z_sv4s= i > + (*__addr, __offset, __p); > return result; > } >=20 > @@ -13973,8 +13973,8 @@ __attribute__ ((__always_inline__, > __gnu_inline__, __artificial__)) > __arm_vldrwq_gather_base_wb_z_u32 (uint32x4_t * __addr, const int > __offset, mve_pred16_t __p) { > uint32x4_t > - result =3D __builtin_mve_vldrwq_gather_base_wb_z_uv4si (*__addr, > __offset, __p); > - __addr +=3D __offset; > + result =3D __builtin_mve_vldrwq_gather_base_nowb_z_uv4si (*__addr, > + __offset, __p); *__addr =3D __builtin_mve_vldrwq_gather_base_wb_z_uv4s= i > + (*__addr, __offset, __p); > return result; > } >=20 > @@ -19372,8 +19372,8 @@ __attribute__ ((__always_inline__, > __gnu_inline__, __artificial__)) > __arm_vldrwq_gather_base_wb_f32 (uint32x4_t * __addr, const int __offset= ) > { > float32x4_t > - result =3D __builtin_mve_vldrwq_gather_base_wb_fv4sf (*__addr, __offse= t); > - __addr +=3D __offset; > + result =3D __builtin_mve_vldrwq_gather_base_nowb_fv4sf (*__addr, > + __offset); *__addr =3D __builtin_mve_vldrwq_gather_base_wb_fv4sf > + (*__addr, __offset); > return result; > } >=20 > @@ -19382,8 +19382,8 @@ __attribute__ ((__always_inline__, > __gnu_inline__, __artificial__)) > __arm_vldrwq_gather_base_wb_z_f32 (uint32x4_t * __addr, const int > __offset, mve_pred16_t __p) { > float32x4_t > - result =3D __builtin_mve_vldrwq_gather_base_wb_z_fv4sf (*__addr, > __offset, __p); > - __addr +=3D __offset; > + result =3D __builtin_mve_vldrwq_gather_base_nowb_z_fv4sf (*__addr, > + __offset, __p); *__addr =3D __builtin_mve_vldrwq_gather_base_wb_z_fv4s= f > + (*__addr, __offset, __p); > return result; > } >=20 > diff --git a/gcc/config/arm/arm_mve_builtins.def > b/gcc/config/arm/arm_mve_builtins.def > index > 2fb975944b9fdac9de4b5a1bec3962be410637f1..753e40a951d071c1ab77476 > a1cc4779e91689178 100644 > --- a/gcc/config/arm/arm_mve_builtins.def > +++ b/gcc/config/arm/arm_mve_builtins.def > @@ -847,16 +847,26 @@ VAR1 (STRSBWBS, vstrdq_scatter_base_wb_s, v2di) > VAR1 (STRSBWBS_P, vstrwq_scatter_base_wb_p_s, v4si) > VAR1 (STRSBWBS_P, vstrwq_scatter_base_wb_p_f, v4sf) > VAR1 (STRSBWBS_P, vstrdq_scatter_base_wb_p_s, v2di) > -VAR1 (LDRGBWBU_Z, vldrwq_gather_base_wb_z_u, v4si) > -VAR1 (LDRGBWBU_Z, vldrdq_gather_base_wb_z_u, v2di) > -VAR1 (LDRGBWBU, vldrwq_gather_base_wb_u, v4si) > -VAR1 (LDRGBWBU, vldrdq_gather_base_wb_u, v2di) > -VAR1 (LDRGBWBS_Z, vldrwq_gather_base_wb_z_s, v4si) > -VAR1 (LDRGBWBS_Z, vldrwq_gather_base_wb_z_f, v4sf) > -VAR1 (LDRGBWBS_Z, vldrdq_gather_base_wb_z_s, v2di) > -VAR1 (LDRGBWBS, vldrwq_gather_base_wb_s, v4si) > -VAR1 (LDRGBWBS, vldrwq_gather_base_wb_f, v4sf) > -VAR1 (LDRGBWBS, vldrdq_gather_base_wb_s, v2di) > +VAR1 (LDRGBWBU_Z, vldrwq_gather_base_nowb_z_u, v4si) > +VAR1 (LDRGBWBU_Z, vldrdq_gather_base_nowb_z_u, v2di) > +VAR1 (LDRGBWBU, vldrwq_gather_base_nowb_u, v4si) > +VAR1 (LDRGBWBU, vldrdq_gather_base_nowb_u, v2di) > +VAR1 (LDRGBWBS_Z, vldrwq_gather_base_nowb_z_s, v4si) > +VAR1 (LDRGBWBS_Z, vldrwq_gather_base_nowb_z_f, v4sf) > +VAR1 (LDRGBWBS_Z, vldrdq_gather_base_nowb_z_s, v2di) > +VAR1 (LDRGBWBS, vldrwq_gather_base_nowb_s, v4si) > +VAR1 (LDRGBWBS, vldrwq_gather_base_nowb_f, v4sf) > +VAR1 (LDRGBWBS, vldrdq_gather_base_nowb_s, v2di) > +VAR1 (LDRGBWBXU_Z, vldrdq_gather_base_wb_z_s, v2di) > +VAR1 (LDRGBWBXU_Z, vldrdq_gather_base_wb_z_u, v2di) > +VAR1 (LDRGBWBXU, vldrdq_gather_base_wb_s, v2di) > +VAR1 (LDRGBWBXU, vldrdq_gather_base_wb_u, v2di) > +VAR1 (LDRGBWBXU_Z, vldrwq_gather_base_wb_z_s, v4si) > +VAR1 (LDRGBWBXU_Z, vldrwq_gather_base_wb_z_f, v4sf) > +VAR1 (LDRGBWBXU_Z, vldrwq_gather_base_wb_z_u, v4si) > +VAR1 (LDRGBWBXU, vldrwq_gather_base_wb_s, v4si) > +VAR1 (LDRGBWBXU, vldrwq_gather_base_wb_f, v4sf) > +VAR1 (LDRGBWBXU, vldrwq_gather_base_wb_u, v4si) > VAR1 (BINOP_NONE_NONE_NONE, vadciq_s, v4si) > VAR1 (BINOP_UNONE_UNONE_UNONE, vadciq_u, v4si) > VAR1 (BINOP_NONE_NONE_NONE, vadcq_s, v4si) diff --git > a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index > df602b07840bb4ccb9aa2a9b10992ba7078452ba..d1028f4542b4972b4080e46 > 544c86d625d77383a 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -10420,6 +10420,20 @@ > (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] > "TARGET_HAVE_MVE" > { > + rtx ignore_result =3D gen_reg_rtx (V4SImode); > + emit_insn ( > + gen_mve_vldrwq_gather_base_wb_v4si_insn (ignore_result, > operands[0], > + operands[1], operands[2])); > + DONE; > +}) > + > +(define_expand "mve_vldrwq_gather_base_nowb_v4si" > + [(match_operand:V4SI 0 "s_register_operand") > + (match_operand:V4SI 1 "s_register_operand") > + (match_operand:SI 2 "mve_vldrd_immediate") > + (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] > + "TARGET_HAVE_MVE" > +{ > rtx ignore_wb =3D gen_reg_rtx (V4SImode); > emit_insn ( > gen_mve_vldrwq_gather_base_wb_v4si_insn (operands[0], > ignore_wb, @@ -10459,6 +10473,21 @@ > (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] > "TARGET_HAVE_MVE" > { > + rtx ignore_result =3D gen_reg_rtx (V4SImode); > + emit_insn ( > + gen_mve_vldrwq_gather_base_wb_z_v4si_insn (ignore_result, > operands[0], > + operands[1], operands[2], > + operands[3])); > + DONE; > +}) > +(define_expand "mve_vldrwq_gather_base_nowb_z_v4si" > + [(match_operand:V4SI 0 "s_register_operand") > + (match_operand:V4SI 1 "s_register_operand") > + (match_operand:SI 2 "mve_vldrd_immediate") > + (match_operand:HI 3 "vpr_register_operand") > + (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] > + "TARGET_HAVE_MVE" > +{ > rtx ignore_wb =3D gen_reg_rtx (V4SImode); > emit_insn ( > gen_mve_vldrwq_gather_base_wb_z_v4si_insn (operands[0], > ignore_wb, @@ -10487,12 +10516,26 @@ > ops[0] =3D operands[0]; > ops[1] =3D operands[2]; > ops[2] =3D operands[3]; > - output_asm_insn ("vpst\;\tvldrwt.u32\t%q0, [%q1, %2]!",ops); > + output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops); > return ""; > } > [(set_attr "length" "8")]) >=20 > (define_expand "mve_vldrwq_gather_base_wb_fv4sf" > + [(match_operand:V4SI 0 "s_register_operand") > + (match_operand:V4SI 1 "s_register_operand") > + (match_operand:SI 2 "mve_vldrd_immediate") > + (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] > + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > +{ > + rtx ignore_result =3D gen_reg_rtx (V4SFmode); > + emit_insn ( > + gen_mve_vldrwq_gather_base_wb_fv4sf_insn (ignore_result, operands[0], > + operands[1], operands[2])); > + DONE; > +}) > + > +(define_expand "mve_vldrwq_gather_base_nowb_fv4sf" > [(match_operand:V4SF 0 "s_register_operand") > (match_operand:V4SI 1 "s_register_operand") > (match_operand:SI 2 "mve_vldrd_immediate") @@ -10531,6 +10574,22 > @@ > [(set_attr "length" "4")]) >=20 > (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf" > + [(match_operand:V4SI 0 "s_register_operand") > + (match_operand:V4SI 1 "s_register_operand") > + (match_operand:SI 2 "mve_vldrd_immediate") > + (match_operand:HI 3 "vpr_register_operand") > + (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] > + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > +{ > + rtx ignore_result =3D gen_reg_rtx (V4SFmode); > + emit_insn ( > + gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (ignore_result, > operands[0], > + operands[1], operands[2], > + operands[3])); > + DONE; > +}) > + > +(define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf" > [(match_operand:V4SF 0 "s_register_operand") > (match_operand:V4SI 1 "s_register_operand") > (match_operand:SI 2 "mve_vldrd_immediate") @@ -10566,7 +10625,7 > @@ > ops[0] =3D operands[0]; > ops[1] =3D operands[2]; > ops[2] =3D operands[3]; > - output_asm_insn ("vpst\;\tvldrwt.u32\t%q0, [%q1, %2]!",ops); > + output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops); > return ""; > } > [(set_attr "length" "8")]) > @@ -10578,6 +10637,20 @@ > (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] > "TARGET_HAVE_MVE" > { > + rtx ignore_result =3D gen_reg_rtx (V2DImode); > + emit_insn ( > + gen_mve_vldrdq_gather_base_wb_v2di_insn (ignore_result, > operands[0], > + operands[1], operands[2])); > + DONE; > +}) > + > +(define_expand "mve_vldrdq_gather_base_nowb_v2di" > + [(match_operand:V2DI 0 "s_register_operand") > + (match_operand:V2DI 1 "s_register_operand") > + (match_operand:SI 2 "mve_vldrd_immediate") > + (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] > + "TARGET_HAVE_MVE" > +{ > rtx ignore_wb =3D gen_reg_rtx (V2DImode); > emit_insn ( > gen_mve_vldrdq_gather_base_wb_v2di_insn (operands[0], > ignore_wb, @@ -10585,6 +10658,7 @@ > DONE; > }) >=20 > + > ;; > ;; [vldrdq_gather_base_wb_s vldrdq_gather_base_wb_u] ;; @@ -10617,6 > +10691,22 @@ > (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] > "TARGET_HAVE_MVE" > { > + rtx ignore_result =3D gen_reg_rtx (V2DImode); > + emit_insn ( > + gen_mve_vldrdq_gather_base_wb_z_v2di_insn (ignore_result, > operands[0], > + operands[1], operands[2], > + operands[3])); > + DONE; > +}) > + > +(define_expand "mve_vldrdq_gather_base_nowb_z_v2di" > + [(match_operand:V2DI 0 "s_register_operand") > + (match_operand:V2DI 1 "s_register_operand") > + (match_operand:SI 2 "mve_vldrd_immediate") > + (match_operand:HI 3 "vpr_register_operand") > + (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] > + "TARGET_HAVE_MVE" > +{ > rtx ignore_wb =3D gen_reg_rtx (V2DImode); > emit_insn ( > gen_mve_vldrdq_gather_base_wb_z_v2di_insn (operands[0], > ignore_wb, @@ -10660,7 +10750,7 @@ > ops[0] =3D operands[0]; > ops[1] =3D operands[2]; > ops[2] =3D operands[3]; > - output_asm_insn ("vpst\;\tvldrdt.u64\t%q0, [%q1, %2]!",ops); > + output_asm_insn ("vpst\;vldrdt.u64\t%q0, [%q1, %2]!",ops); > return ""; > } > [(set_attr "length" "8")]) > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c > index > a5c5a61345cb0a46abc7796ceff195698cabe804..0d1ee769ec64b55c7559ce9d > c14f8a6ae2e43e34 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_ > +++ s64.c > @@ -10,4 +10,6 @@ foo (uint64x2_t * addr) > return vldrdq_gather_base_wb_s64 (addr, 8); } >=20 > -/* { dg-final { scan-assembler "vldrd.64" } } */ > +/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > +/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, > +#\[0-9\]+\\\]!" } } */ > +/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64. > c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64. > c > index > 442bca92a43c05124717bf6ea0c44672941091f0..cb2a41bdcd32b553a93d3bcc > 4787d506f1b54f74 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64. > c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_ > +++ u64.c > @@ -10,4 +10,6 @@ foo (uint64x2_t * addr) > return vldrdq_gather_base_wb_u64 (addr, 8); } >=20 > -/* { dg-final { scan-assembler "vldrd.64" } } */ > +/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > +/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, > +#\[0-9\]+\\\]!" } } */ > +/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s6 > 4.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s6 > 4.c > index > 1863d0835e12328b7b7bb824f59e3d441042f56d..243fbeacc3429025202da2ff > 157ade38a472e123 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s6 > 4.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_ > +++ z_s64.c > @@ -8,4 +8,8 @@ int64x2_t foo (uint64x2_t * addr, mve_pred16_t p) > return vldrdq_gather_base_wb_z_s64 (addr, 1016, p); } >=20 > -/* { dg-final { scan-assembler "vldrdt.u64" } } */ > +/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > +/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*$" } } */ > +/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, > +#\[0-9\]+\\\]!" } } */ > +/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u6 > 4.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u6 > 4.c > index > 7ba272a112607b0e57a3d4659e5b4033044af83c..10ba42405fe8fde9d4f8993 > b20e41a59c7bb2e77 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u6 > 4.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_ > +++ z_u64.c > @@ -8,4 +8,8 @@ uint64x2_t foo (uint64x2_t * addr, mve_pred16_t p) > return vldrdq_gather_base_wb_z_u64 (addr, 8, p); } >=20 > -/* { dg-final { scan-assembler "vldrdt.u64" } } */ > +/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > +/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ > +/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, > +#\[0-9\]+\\\]!" } } */ > +/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32. > c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32. > c > index > 6b496873f173e30414ffcddf50513758bc8ca770..db8108e37325c4e1fafd2293d > 48eba0c33309073 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32. > c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_ > +++ f32.c > @@ -10,4 +10,6 @@ foo (uint32x4_t * addr) > return vldrwq_gather_base_wb_f32 (addr, 8); } >=20 > -/* { dg-final { scan-assembler "vldrw.u32" } } */ > +/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > +/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, > +#\[0-9\]+\\\]!" } } */ > +/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32. > c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32. > c > index > 9bbbd0d701546b5ec224129aef49e632addea550..3da64e218e2c0789e996be > 551650033567eba4e5 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32. > c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_ > +++ s32.c > @@ -10,4 +10,6 @@ foo (uint32x4_t * addr) > return vldrwq_gather_base_wb_s32 (addr, 8); } >=20 > -/* { dg-final { scan-assembler "vldrw.u32" } } */ > +/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > +/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, > +#\[0-9\]+\\\]!" } } */ > +/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32. > c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32. > c > index > 774230b290367a7d28f0c8579be26fc9c75db1cb..2597ee11608bfe21d697f225 > 0bee7e69c0cc7aec 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32. > c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_ > +++ u32.c > @@ -10,4 +10,6 @@ foo (uint32x4_t * addr) > return vldrwq_gather_base_wb_u32 (addr, 8); } >=20 > -/* { dg-final { scan-assembler "vldrw.u32" } } */ > +/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > +/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, > +#\[0-9\]+\\\]!" } } */ > +/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f3 > 2.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f3 > 2.c > index > 6400f014a88ccf34fef15effff65f9b1267dbd5f..f1ba63855be254d96806c16317 > 7e32856294c106 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f3 > 2.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_ > +++ z_f32.c > @@ -10,4 +10,8 @@ foo (uint32x4_t * addr, mve_pred16_t p) > return vldrwq_gather_base_wb_z_f32 (addr, 8, p); } >=20 > -/* { dg-final { scan-assembler "vldrwt.u32" } } */ > +/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > +/* { dg-final { scan-assembler "vmsr\tP0, r\[0-9\]+.*" } } */ > +/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, > +#\[0-9\]+\\\]!" } } */ > +/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s3 > 2.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s3 > 2.c > index > de7006c51f17665b80b83fd5ea034477b7a7e778..56da5a46c64d2946ceade86 > 89105048e19efdc6a 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s3 > 2.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_ > +++ z_s32.c > @@ -10,4 +10,8 @@ foo (uint32x4_t * addr, mve_pred16_t p) > return vldrwq_gather_base_wb_z_s32 (addr, 8, p); } >=20 > -/* { dg-final { scan-assembler "vldrwt.u32" } } */ > +/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > +/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ > +/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, > +#\[0-9\]+\\\]!" } } */ > +/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u3 > 2.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u > 32.c > index > 6c9608f07ba966876804f56403a4352a51a0e0c4..63165d97c1a7b4120be0363 > 48a09b73afddd36d1 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u3 > 2.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_ > +++ z_u32.c > @@ -10,4 +10,8 @@ foo (uint32x4_t * addr, mve_pred16_t p) > return vldrwq_gather_base_wb_z_u32 (addr, 8, p); } >=20 > -/* { dg-final { scan-assembler "vldrwt.u32" } } */ > +/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */ > +/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ > +/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, > +#\[0-9\]+\\\]!" } } */ > +/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } > +} */