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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable >From afa416dab831795f7e1114da2fb9e94ea3b8c519 Mon Sep 17 00:00:00 2001=0A= From: oluade01 =0A= Date: Fri, 14 Apr 2023 15:10:07 +0100=0A= Subject: [PATCH 2/4] AArch64: New RTL for ABD=0A= =0A= This patch adds new RTL and tests for sabd and uabd=0A= =0A= PR tree-optimization/109156=0A= =0A= gcc/ChangeLog:=0A= =0A= * config/aarch64/aarch64-simd-builtins.def (sabd, uabd):=0A= Change the mode to 3.=0A= * config/aarch64/aarch64-simd.md (aarch64_abd):=0A= Rename to abd3.=0A= * config/aarch64/aarch64-sve.md (abd_3): Rename=0A= to abd3.=0A= =0A= gcc/testsuite/ChangeLog:=0A= =0A= * gcc.target/aarch64/abd.h: New file.=0A= * gcc.target/aarch64/abd_2.c: New test.=0A= * gcc.target/aarch64/abd_3.c: New test.=0A= * gcc.target/aarch64/abd_4.c: New test.=0A= * gcc.target/aarch64/abd_run_1.c: New test.=0A= * gcc.target/aarch64/sve/sve/abd_1.c: New test.=0A= * gcc.target/aarch64/sve/sve/abd_2.c: New test.=0A= ---=0A= gcc/config/aarch64/aarch64-simd-builtins.def | 6 +-=0A= gcc/config/aarch64/aarch64-simd.md | 4 +-=0A= gcc/config/aarch64/aarch64-sve.md | 4 +-=0A= gcc/testsuite/gcc.target/aarch64/abd.h | 62 +++++++++++++=0A= gcc/testsuite/gcc.target/aarch64/abd_2.c | 34 +++++++=0A= gcc/testsuite/gcc.target/aarch64/abd_3.c | 34 +++++++=0A= gcc/testsuite/gcc.target/aarch64/abd_4.c | 33 +++++++=0A= gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 93 ++++++++++++++++++++=0A= gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 34 +++++++=0A= gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 33 +++++++=0A= 10 files changed, 330 insertions(+), 7 deletions(-)=0A= create mode 100644 gcc/testsuite/gcc.target/aarch64/abd.h=0A= create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_2.c=0A= create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_3.c=0A= create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_4.c=0A= create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_run_1.c=0A= create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_1.c=0A= create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_2.c=0A= =0A= diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarc= h64/aarch64-simd-builtins.def=0A= index 1beaa08c1e7c94bc13a64865ddb677345534699c..3efbf0a1874f6242e69665b8316= d9a7d62a9c8cf 100644=0A= --- a/gcc/config/aarch64/aarch64-simd-builtins.def=0A= +++ b/gcc/config/aarch64/aarch64-simd-builtins.def=0A= @@ -194,9 +194,9 @@=0A= BUILTIN_VDQV_L (UNOP, saddlv, 0, NONE)=0A= BUILTIN_VDQV_L (UNOPU, uaddlv, 0, NONE)=0A= =0A= - /* Implemented by aarch64_abd. */=0A= - BUILTIN_VDQ_BHSI (BINOP, sabd, 0, NONE)=0A= - BUILTIN_VDQ_BHSI (BINOPU, uabd, 0, NONE)=0A= + /* Implemented by abd3. */=0A= + BUILTIN_VDQ_BHSI (BINOP, sabd, 3, NONE)=0A= + BUILTIN_VDQ_BHSI (BINOPU, uabd, 3, NONE)=0A= =0A= /* Implemented by aarch64_aba. */=0A= BUILTIN_VDQ_BHSI (TERNOP, saba, 0, NONE)=0A= diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch6= 4-simd.md=0A= index cb2223d29c2d97d6d396b4eca166463369819ca6..f52c148a80589a48befb71135e9= 0aa02a2b253e7 100644=0A= --- a/gcc/config/aarch64/aarch64-simd.md=0A= +++ b/gcc/config/aarch64/aarch64-simd.md=0A= @@ -915,7 +915,7 @@ (define_insn "aarch64_abs"=0A= ;; So (ABS:QI (minus:QI 64 -128)) =3D=3D (ABS:QI (192 or -64 signed)) =3D= =3D 64.=0A= ;; Whereas SABD would return 192 (-64 signed) on the above example.=0A= ;; Use MINUS ([us]max (op1, op2), [us]min (op1, op2)) instead.=0A= -(define_insn "aarch64_abd"=0A= +(define_insn "abd3"=0A= [(set (match_operand:VDQ_BHSI 0 "register_operand" "=3Dw")=0A= (minus:VDQ_BHSI=0A= (USMAX:VDQ_BHSI=0A= @@ -1080,7 +1080,7 @@ (define_expand "sadv16qi"=0A= {=0A= rtx ones =3D force_reg (V16QImode, CONST1_RTX (V16QImode));=0A= rtx abd =3D gen_reg_rtx (V16QImode);=0A= - emit_insn (gen_aarch64_abdv16qi (abd, operands[1], operands[2]));=0A= + emit_insn (gen_abdv16qi3 (abd, operands[1], operands[2]));=0A= emit_insn (gen_udot_prodv16qi (operands[0], abd, ones, operands[3]));=0A= DONE;=0A= }=0A= diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64= -sve.md=0A= index 4b4c02c90fec6ce1ff15a8b2a5df348224a307b7..5966a33a3cc471f8c2e875b9e3a= 6a8a8ddc6af17 100644=0A= --- a/gcc/config/aarch64/aarch64-sve.md=0A= +++ b/gcc/config/aarch64/aarch64-sve.md=0A= @@ -4001,7 +4001,7 @@ (define_insn_and_rewrite "*aarch64_adr_shift_uxtw"=0A= ;; -----------------------------------------------------------------------= --=0A= =0A= ;; Unpredicated integer absolute difference.=0A= -(define_expand "abd_3"=0A= +(define_expand "abd3"=0A= [(use (match_operand:SVE_I 0 "register_operand"))=0A= (USMAX:SVE_I=0A= (match_operand:SVE_I 1 "register_operand")=0A= @@ -6973,7 +6973,7 @@ (define_expand "sad"=0A= {=0A= rtx ones =3D force_reg (mode, CONST1_RTX (mode));=0A= rtx diff =3D gen_reg_rtx (mode);=0A= - emit_insn (gen_abd_3 (diff, operands[1], operands[2]));=0A= + emit_insn (gen_abd3 (diff, operands[1], operands[2]));=0A= emit_insn (gen_udot_prod (operands[0], diff, ones, operands[3]= ));=0A= DONE;=0A= }=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/abd.h b/gcc/testsuite/gcc.tar= get/aarch64/abd.h=0A= new file mode 100644=0A= index 0000000000000000000000000000000000000000..bc38e8508056cf2623cddd6053b= f1cec3fa4ece4=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/aarch64/abd.h=0A= @@ -0,0 +1,62 @@=0A= +#ifdef ABD_IDIOM=0A= +=0A= +#define TEST1(S, TYPE) \=0A= +void fn_##S##_##TYPE (S TYPE * restrict a, \=0A= + S TYPE * restrict b, \=0A= + S TYPE * restrict out) { \=0A= + for (int i =3D 0; i < N; i++) { \=0A= + signed TYPE diff =3D b[i] - a[i]; \=0A= + out[i] =3D diff > 0 ? diff : -diff; \=0A= +} }=0A= +=0A= +#define TEST2(S, TYPE1, TYPE2) \=0A= +void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \=0A= + (S TYPE1 * restrict a, \=0A= + S TYPE1 * restrict b, \=0A= + S TYPE2 * restrict out) { \=0A= + for (int i =3D 0; i < N; i++) { \=0A= + signed TYPE2 diff =3D b[i] - a[i]; \=0A= + out[i] =3D diff > 0 ? diff : -diff; \=0A= +} }=0A= +=0A= +#define TEST3(S, TYPE1, TYPE2, TYPE3) \=0A= +void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \=0A= + (S TYPE1 * restrict a, \=0A= + S TYPE2 * restrict b, \=0A= + S TYPE3 * restrict out) { \=0A= + for (int i =3D 0; i < N; i++) { \=0A= + signed TYPE3 diff =3D b[i] - a[i]; \=0A= + out[i] =3D diff > 0 ? diff : -diff; \=0A= +} }=0A= +=0A= +#endif=0A= +=0A= +#ifdef ABD_ABS=0A= +=0A= +#define TEST1(S, TYPE) \=0A= +void fn_##S##_##TYPE (S TYPE * restrict a, \=0A= + S TYPE * restrict b, \=0A= + S TYPE * restrict out) { \=0A= + for (int i =3D 0; i < N; i++) \=0A= + out[i] =3D __builtin_abs(a[i] - b[i]); \=0A= +}=0A= +=0A= +#define TEST2(S, TYPE1, TYPE2) \=0A= +void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \=0A= + (S TYPE1 * restrict a, \=0A= + S TYPE1 * restrict b, \=0A= + S TYPE2 * restrict out) { \=0A= + for (int i =3D 0; i < N; i++) \=0A= + out[i] =3D __builtin_abs(a[i] - b[i]); \=0A= +}=0A= +=0A= +#define TEST3(S, TYPE1, TYPE2, TYPE3) \=0A= +void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \=0A= + (S TYPE1 * restrict a, \=0A= + S TYPE2 * restrict b, \=0A= + S TYPE3 * restrict out) { \=0A= + for (int i =3D 0; i < N; i++) \=0A= + out[i] =3D __builtin_abs(a[i] - b[i]); \=0A= +}=0A= +=0A= +#endif=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.t= arget/aarch64/abd_2.c=0A= new file mode 100644=0A= index 0000000000000000000000000000000000000000..45bcfabe05a395f6775f78f28c7= 3eb536ba5654e=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c=0A= @@ -0,0 +1,34 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O3" } */=0A= +=0A= +#pragma GCC target "+nosve"=0A= +#define N 1024=0A= +=0A= +#define ABD_ABS=0A= +#include "abd.h"=0A= +=0A= +TEST1(signed, int)=0A= +TEST1(signed, short)=0A= +TEST1(signed, char)=0A= +=0A= +TEST2(signed, char, int)=0A= +TEST2(signed, char, short)=0A= +=0A= +TEST3(signed, char, int, short)=0A= +TEST3(signed, char, short, int)=0A= +=0A= +TEST1(unsigned, int)=0A= +TEST1(unsigned, short)=0A= +TEST1(unsigned, char)=0A= +=0A= +TEST2(unsigned, char, int)=0A= +TEST2(unsigned, char, short)=0A= +=0A= +TEST3(unsigned, char, int, short)=0A= +TEST3(unsigned, char, short, int)=0A= +=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s,= v\[0-9\]+\.4s" 2 } } */=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h,= v\[0-9\]+\.8h" 1 } } */=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16= b, v\[0-9\]+\.16b" 1 } } */=0A= +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h,= v\[0-9\]+\.8h" 1 } } */=0A= +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16= b, v\[0-9\]+\.16b" 1 } } */=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/abd_3.c b/gcc/testsuite/gcc.t= arget/aarch64/abd_3.c=0A= new file mode 100644=0A= index 0000000000000000000000000000000000000000..e7079cdd4a3e37c9e22f89cff30= 1451be1441bc2=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/aarch64/abd_3.c=0A= @@ -0,0 +1,34 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-Ofast" } */=0A= +=0A= +#pragma GCC target "arch=3Darmv8-a"=0A= +#define N 1024=0A= +=0A= +#define ABD_ABS=0A= +#include "abd.h"=0A= +=0A= +TEST1(signed, int)=0A= +TEST1(signed, short)=0A= +TEST1(signed, char)=0A= +=0A= +TEST2(signed, char, int)=0A= +TEST2(signed, char, short)=0A= +=0A= +TEST3(signed, char, int, short)=0A= +TEST3(signed, char, short, int)=0A= +=0A= +TEST1(unsigned, int)=0A= +TEST1(unsigned, short)=0A= +TEST1(unsigned, char)=0A= +=0A= +TEST2(unsigned, char, int)=0A= +TEST2(unsigned, char, short)=0A= +=0A= +TEST3(unsigned, char, int, short)=0A= +TEST3(unsigned, char, short, int)=0A= +=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s,= v\[0-9\]+\.4s" 2 } } */=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h,= v\[0-9\]+\.8h" 1 } } */=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16= b, v\[0-9\]+\.16b" 1 } } */=0A= +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h,= v\[0-9\]+\.8h" 1 } } */=0A= +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16= b, v\[0-9\]+\.16b" 1 } } */=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/abd_4.c b/gcc/testsuite/gcc.t= arget/aarch64/abd_4.c=0A= new file mode 100644=0A= index 0000000000000000000000000000000000000000..da9598193aec72fa40a02d25d88= e7c31a39153f7=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/aarch64/abd_4.c=0A= @@ -0,0 +1,33 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O3" } */=0A= +=0A= +#pragma GCC target "+nosve"=0A= +#define N 1024=0A= +=0A= +#define ABD_IDIOM=0A= +#include "abd.h"=0A= +=0A= +TEST1(signed, int)=0A= +TEST1(signed, short)=0A= +TEST1(signed, char)=0A= +=0A= +TEST2(signed, char, int)=0A= +TEST2(signed, char, short)=0A= +=0A= +TEST3(signed, char, int, short)=0A= +TEST3(signed, char, short, int)=0A= +=0A= +TEST1(unsigned, int)=0A= +TEST1(unsigned, short)=0A= +TEST1(unsigned, char)=0A= +=0A= +TEST2(unsigned, char, int)=0A= +TEST2(unsigned, char, short)=0A= +=0A= +TEST3(unsigned, char, int, short)=0A= +TEST3(unsigned, char, short, int)=0A= +=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s,= v\[0-9\]+\.4s" 2 } } */=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h,= v\[0-9\]+\.8h" 8 } } */=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16= b, v\[0-9\]+\.16b" 2 } } */=0A= +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h,= v\[0-9\]+\.8h" 2 } } */=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c b/gcc/testsuite/g= cc.target/aarch64/abd_run_1.c=0A= new file mode 100644=0A= index 0000000000000000000000000000000000000000..7bb0a801415ffeab235bd636032= 112228255e836=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c=0A= @@ -0,0 +1,93 @@=0A= +/* { dg-do run } */=0A= +/* { dg-options "-O3" } */=0A= +=0A= +#pragma GCC target "+nosve"=0A= +#define N 16=0A= +=0A= +#define ABD_ABS=0A= +#include "abd.h"=0A= +=0A= +TEST1(signed, int)=0A= +TEST1(signed, short)=0A= +TEST1(signed, char)=0A= +=0A= +TEST1(unsigned, int)=0A= +TEST1(unsigned, short)=0A= +TEST1(unsigned, char)=0A= +=0A= +#define EMPTY { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }=0A= +#define sA { -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -= 50, -50, -50, -50 }=0A= +#define uA { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 1= 00, 100, 100, 100 }=0A= +#define B { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25= }=0A= +#define GOLD { 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75,= 75 }=0A= +=0A= +typedef signed char s8;=0A= +typedef unsigned char u8;=0A= +typedef signed short s16;=0A= +typedef unsigned short u16;=0A= +typedef signed int s32;=0A= +typedef unsigned int u32;=0A= +=0A= +s8 sc_out[] =3D EMPTY;=0A= +u8 uc_out[] =3D EMPTY;=0A= +s16 ss_out[] =3D EMPTY;=0A= +u16 us_out[] =3D EMPTY;=0A= +s32 si_out[] =3D EMPTY;=0A= +u32 ui_out[] =3D EMPTY;=0A= +=0A= +s8 sc_A[] =3D sA;=0A= +s8 sc_B[] =3D B;=0A= +u8 uc_A[] =3D uA;=0A= +u8 uc_B[] =3D B;=0A= +=0A= +s16 ss_A[] =3D sA;=0A= +s16 ss_B[] =3D B;=0A= +u16 us_A[] =3D uA;=0A= +u16 us_B[] =3D B;=0A= +=0A= +s32 si_A[] =3D sA;=0A= +s32 si_B[] =3D B;=0A= +u32 ui_A[] =3D uA;=0A= +u32 ui_B[] =3D B;=0A= +=0A= +s8 sc_gold[] =3D GOLD;=0A= +u8 uc_gold[] =3D GOLD;=0A= +s16 ss_gold[] =3D GOLD;=0A= +u16 us_gold[] =3D GOLD;=0A= +s32 si_gold[] =3D GOLD;=0A= +u32 ui_gold[] =3D GOLD;=0A= +=0A= +extern void abort (void);=0A= +=0A= +#define CLEAR(arr) \=0A= +for (int i =3D 0; i < N; i++) \=0A= + arr[i] =3D 0;=0A= +=0A= +#define COMPARE(A, B) \=0A= +for (int i =3D 0; i < N; i++) \=0A= + if (A[i] !=3D B[i]) \=0A= + abort();=0A= +=0A= +int main ()=0A= +{=0A= + fn_signed_char (sc_A, sc_B, sc_out);=0A= + COMPARE (sc_out, sc_gold);=0A= +=0A= + fn_unsigned_char (uc_A, uc_B, uc_out);=0A= + COMPARE (uc_out, uc_gold);=0A= +=0A= + fn_signed_short (ss_A, ss_B, ss_out);=0A= + COMPARE (ss_out, ss_gold)=0A= +=0A= + fn_unsigned_short (us_A, us_B, us_out);=0A= + COMPARE (us_out, us_gold)=0A= +=0A= + fn_signed_int (si_A, si_B, si_out);=0A= + COMPARE (si_out, si_gold);=0A= +=0A= + fn_unsigned_int (ui_A, ui_B, ui_out);=0A= + COMPARE (ui_out, ui_gold);=0A= +=0A= + return 0;=0A= +}=0A= +=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/g= cc.target/aarch64/sve/abd_1.c=0A= new file mode 100644=0A= index 0000000000000000000000000000000000000000..6ba111a623a344877a9d2eabda2= 9a629a0dc8258=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c=0A= @@ -0,0 +1,34 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O3" } */=0A= +=0A= +#pragma GCC target "arch=3Darmv8-a"=0A= +#define N 1024=0A= +=0A= +#define ABD_ABS=0A= +#include "../abd.h"=0A= +=0A= +TEST1(signed, int)=0A= +TEST1(signed, short)=0A= +TEST1(signed, char)=0A= +=0A= +TEST2(signed, char, int)=0A= +TEST2(signed, char, short)=0A= +=0A= +TEST3(signed, char, int, short)=0A= +TEST3(signed, char, short, int)=0A= +=0A= +TEST1(unsigned, int)=0A= +TEST1(unsigned, short)=0A= +TEST1(unsigned, char)=0A= +=0A= +TEST2(unsigned, char, int)=0A= +TEST2(unsigned, char, short)=0A= +=0A= +TEST3(unsigned, char, int, short)=0A= +TEST3(unsigned, char, short, int)=0A= +=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s,= v\[0-9\]+\.4s" 2 } } */=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h,= v\[0-9\]+\.8h" 1 } } */=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16= b, v\[0-9\]+\.16b" 1 } } */=0A= +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h,= v\[0-9\]+\.8h" 1 } } */=0A= +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16= b, v\[0-9\]+\.16b" 1 } } */=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/g= cc.target/aarch64/sve/abd_2.c=0A= new file mode 100644=0A= index 0000000000000000000000000000000000000000..6d4b3fec76279656ebf827c3864= 81337451f82fa=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c=0A= @@ -0,0 +1,33 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O3" } */=0A= +=0A= +#pragma GCC target "arch=3Darmv8-a"=0A= +#define N 1024=0A= +=0A= +#define ABD_IDIOM=0A= +#include "../abd.h"=0A= +=0A= +TEST1(signed, int)=0A= +TEST1(signed, short)=0A= +TEST1(signed, char)=0A= +=0A= +TEST2(signed, char, int)=0A= +TEST2(signed, char, short)=0A= +=0A= +TEST3(signed, char, int, short)=0A= +TEST3(signed, char, short, int)=0A= +=0A= +TEST1(unsigned, int)=0A= +TEST1(unsigned, short)=0A= +TEST1(unsigned, char)=0A= +=0A= +TEST2(unsigned, char, int)=0A= +TEST2(unsigned, char, short)=0A= +=0A= +TEST3(unsigned, char, int, short)=0A= +TEST3(unsigned, char, short, int)=0A= +=0A= +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s,= v\[0-9\]+\.4s" 2 } } */=0A= +/* { dg-final { scan-assembler-times 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