From: Bernd Edlinger <bernd.edlinger@hotmail.de>
To: Richard Biener <rguenther@suse.de>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Richard Earnshaw <richard.earnshaw@arm.com>,
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>,
Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>,
Eric Botcazou <ebotcazou@adacore.com>, Jeff Law <law@redhat.com>,
Jakub Jelinek <jakub@redhat.com>
Subject: [PATCHv4] Fix not 8-byte aligned ldrd/strd on ARMv5 (PR 89544)
Date: Thu, 08 Aug 2019 14:20:00 -0000 [thread overview]
Message-ID: <DB8PR10MB2569255E3191B5C7FA70D338E4D70@DB8PR10MB2569.EURPRD10.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <AM6PR10MB2566A6E51DC500187D9EC6CFE4D90@AM6PR10MB2566.EURPRD10.PROD.OUTLOOK.COM>
[-- Attachment #1: Type: text/plain, Size: 8179 bytes --]
On 8/2/19 9:01 PM, Bernd Edlinger wrote:
> On 8/2/19 3:11 PM, Richard Biener wrote:
>> On Tue, 30 Jul 2019, Bernd Edlinger wrote:
>>
>>>
>>> I have no test coverage for the movmisalign optab though, so I
>>> rely on your code review for that part.
>>
>> It looks OK. I tried to make it trigger on the following on
>> i?86 with -msse2:
>>
>> typedef int v4si __attribute__((vector_size (16)));
>>
>> struct S { v4si v; } __attribute__((packed));
>>
>> v4si foo (struct S s)
>> {
>> return s.v;
>> }
>>
>
> Hmm, the entry_parm need to be a MEM_P and an unaligned one.
> So the test case could be made to trigger it this way:
>
> typedef int v4si __attribute__((vector_size (16)));
>
> struct S { v4si v; } __attribute__((packed));
>
> int t;
> v4si foo (struct S a, struct S b, struct S c, struct S d,
> struct S e, struct S f, struct S g, struct S h,
> int i, int j, int k, int l, int m, int n,
> int o, struct S s)
> {
> t = o;
> return s.v;
> }
>
Ah, I realized that there are already a couple of very similar
test cases: gcc.target/i386/pr35767-1.c, gcc.target/i386/pr35767-1d.c,
gcc.target/i386/pr35767-1i.c and gcc.target/i386/pr39445.c,
which also manage to execute the movmisalign code with the latest patch
version. So I thought that it is not necessary to add another one.
> However the code path is still not reached, since targetm.slow_ualigned_access
> is always FALSE, which is probably a flaw in my patch.
>
> So I think,
>
> + else if (MEM_P (data->entry_parm)
> + && GET_MODE_ALIGNMENT (promoted_nominal_mode)
> + > MEM_ALIGN (data->entry_parm)
> + && targetm.slow_unaligned_access (promoted_nominal_mode,
> + MEM_ALIGN (data->entry_parm)))
>
> should probably better be
>
> + else if (MEM_P (data->entry_parm)
> + && GET_MODE_ALIGNMENT (promoted_nominal_mode)
> + > MEM_ALIGN (data->entry_parm)
> + && (((icode = optab_handler (movmisalign_optab, promoted_nominal_mode))
> + != CODE_FOR_nothing)
> + || targetm.slow_unaligned_access (promoted_nominal_mode,
> + MEM_ALIGN (data->entry_parm))))
>
> Right?
>
> Then the modified test case would use the movmisalign optab.
> However nothing changes in the end, since the i386 back-end is used to work
> around the middle end not using movmisalign optab when it should do so.
>
I prefer the second form of the check, as it offers more test coverage,
and is probably more correct than the former.
Note there are more variations of this misalign check in expr.c,
some are somehow odd, like expansion of MEM_REF and VIEW_CONVERT_EXPR:
&& mode != BLKmode
&& align < GET_MODE_ALIGNMENT (mode))
{
if ((icode = optab_handler (movmisalign_optab, mode))
!= CODE_FOR_nothing)
[...]
else if (targetm.slow_unaligned_access (mode, align))
temp = extract_bit_field (temp, GET_MODE_BITSIZE (mode),
0, TYPE_UNSIGNED (TREE_TYPE (exp)),
(modifier == EXPAND_STACK_PARM
? NULL_RTX : target),
mode, mode, false, alt_rtl);
I wonder if they are correct this way, why shouldn't we use the movmisalign
optab if it exists, regardless of TARGET_SLOW_UNALIGNED_ACCESSS ?
> I wonder if I should try to add a gcc_checking_assert to the mov<mode> expand
> patterns that the memory is properly aligned ?
>
Wow, that was a really exciting bug-hunt with those assertions around...
>> @@ -3292,6 +3306,23 @@ assign_parm_setup_reg (struct assign_parm_data_all
>>
>> did_conversion = true;
>> }
>> + else if (MEM_P (data->entry_parm)
>> + && GET_MODE_ALIGNMENT (promoted_nominal_mode)
>> + > MEM_ALIGN (data->entry_parm)
>>
>> we arrive here by-passing
>>
>> else if (need_conversion)
>> {
>> /* We did not have an insn to convert directly, or the sequence
>> generated appeared unsafe. We must first copy the parm to a
>> pseudo reg, and save the conversion until after all
>> parameters have been moved. */
>>
>> int save_tree_used;
>> rtx tempreg = gen_reg_rtx (GET_MODE (data->entry_parm));
>>
>> emit_move_insn (tempreg, validated_mem);
>>
>> but this move instruction is invalid in the same way as the case
>> you fix, no? So wouldn't it be better to do
>>
>
> We could do that, but I supposed that there must be a reason why
> assign_parm_setup_stack gets away with that same:
>
> if (data->promoted_mode != data->nominal_mode)
> {
> /* Conversion is required. */
> rtx tempreg = gen_reg_rtx (GET_MODE (data->entry_parm));
>
> emit_move_insn (tempreg, validize_mem (copy_rtx (data->entry_parm)));
>
>
> So either some back-ends are too permissive with us,
> or there is a reason why promoted_mode != nominal_mode
> does not happen together with unaligned entry_parm.
> In a way that would be a rather unusual ABI.
>
To find out if that ever happens I added a couple of checking
assertions in the arm mov<mode> expand patterns.
So far the assertions did (almost) always hold, so it is likely not
necessary to fiddle with all those naive move instructions here.
So my gut feeling is, leave those places alone until there is a reason
for changing them.
However the assertion in movsi triggered a couple times in the
ada testsuite due to expand_builtin_init_descriptor using a
BLKmode MEM rtx, which is only 8-bit aligned. So, I set the
ptr_mode alignment there explicitly.
Several struct-layout-1.dg testcase tripped over misaligned
complex_cst constants, fixed by varasm.c (align_variable).
This is likely a wrong code bug, because misaligned complex
constants, are expanded to misaligned MEM_REF, but the
expansion cannot handle misaligned constants, only packed
structure fields.
Furthermore gcc.dg/Warray-bounds-33.c was fixed by the
change in expr.c (expand_expr_real_1). Certainly is it invalid
to read memory at a function address, but it should not ICE.
The problem here, is the MEM_REF has no valid MEM_ALIGN, it looks
like A32, so the misaligned code execution is not taken, but it is
set to A8 below, but then we hit an ICE if the result is used:
/* Don't set memory attributes if the base expression is
SSA_NAME that got expanded as a MEM. In that case, we should
just honor its original memory attributes. */
if (TREE_CODE (tem) != SSA_NAME || !MEM_P (orig_op0))
set_mem_attributes (op0, exp, 0);
Finally gcc.dg/torture/pr48493.c required the change
in assign_parm_setup_stack. This is just not using the
correct MEM_ALIGN attribute value, while the memory is
actually aligned. Note that set_mem_attributes does not
always preserve the MEM_ALIGN of the ref, since:
/* Default values from pre-existing memory attributes if present. */
refattrs = MEM_ATTRS (ref);
if (refattrs)
{
/* ??? Can this ever happen? Calling this routine on a MEM that
already carries memory attributes should probably be invalid. */
attrs.expr = refattrs->expr;
attrs.offset_known_p = refattrs->offset_known_p;
attrs.offset = refattrs->offset;
attrs.size_known_p = refattrs->size_known_p;
attrs.size = refattrs->size;
attrs.align = refattrs->align;
}
but if we happen to set_mem_align to _exactly_ the MODE_ALIGNMENT
the MEM_ATTRS are zero, and a smaller alignment may result.
Well with those checks in place it should now be a lot harder to generate
invalid code on STRICT_ALIGNMENT targets, without running into an ICE.
Attached is the latest version of my arm alignment patch.
Boot-strapped and reg-tested on x64_64-pc-linux-gnu and arm-linux-gnueabihf.
Is it OK for trunk?
Thanks
Bernd.
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[-- Attachment #2: patch-arm-align-abi.diff --]
[-- Type: text/x-patch; name="patch-arm-align-abi.diff", Size: 12166 bytes --]
2019-08-05 Bernd Edlinger <bernd.edlinger@hotmail.de>
PR middle-end/89544
* builtins.c (expand_builtin_init_descriptor): Set memory alignment.
* expr.c (expand_expr_real_1): Handle FUNCTION_DECL as unaligned.
* function.c (assign_parm_find_stack_rtl): Use larger alignment
when possible.
(assign_parm_setup_reg): Handle misaligned stack arguments.
(assign_parm_setup_stack): Allocate properly aligned stack slots.
* varasm.c (align_variable): Align constants of misaligned types.
* config/arm/arm.md (movdi, movsi, movhi, movhf, movsf, movdf): Check
strict alignment restrictions on memory addresses.
* config/arm/neon.md (movti, mov<VSTRUCT>, mov<VH>): Likewise.
* config/arm/vec-common.md (mov<VALL>): Likewise.
testsuite:
2019-08-05 Bernd Edlinger <bernd.edlinger@hotmail.de>
PR middle-end/89544
* gcc.target/arm/unaligned-argument-1.c: New test.
* gcc.target/arm/unaligned-argument-2.c: New test.
Index: gcc/builtins.c
===================================================================
--- gcc/builtins.c (revision 274168)
+++ gcc/builtins.c (working copy)
@@ -5756,6 +5756,7 @@ expand_builtin_init_descriptor (tree exp)
r_descr = expand_normal (t_descr);
m_descr = gen_rtx_MEM (BLKmode, r_descr);
MEM_NOTRAP_P (m_descr) = 1;
+ set_mem_align (m_descr, GET_MODE_ALIGNMENT (ptr_mode));
r_func = expand_normal (t_func);
r_chain = expand_normal (t_chain);
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md (revision 274168)
+++ gcc/config/arm/arm.md (working copy)
@@ -5824,6 +5824,12 @@
(match_operand:DI 1 "general_operand"))]
"TARGET_EITHER"
"
+ gcc_checking_assert (!MEM_P (operands[0])
+ || MEM_ALIGN (operands[0])
+ >= GET_MODE_ALIGNMENT (DImode));
+ gcc_checking_assert (!MEM_P (operands[1])
+ || MEM_ALIGN (operands[1])
+ >= GET_MODE_ALIGNMENT (DImode));
if (can_create_pseudo_p ())
{
if (!REG_P (operands[0]))
@@ -6000,6 +6006,12 @@
{
rtx base, offset, tmp;
+ gcc_checking_assert (!MEM_P (operands[0])
+ || MEM_ALIGN (operands[0])
+ >= GET_MODE_ALIGNMENT (SImode));
+ gcc_checking_assert (!MEM_P (operands[1])
+ || MEM_ALIGN (operands[1])
+ >= GET_MODE_ALIGNMENT (SImode));
if (TARGET_32BIT || TARGET_HAVE_MOVT)
{
/* Everything except mem = const or mem = mem can be done easily. */
@@ -6489,6 +6501,12 @@
(match_operand:HI 1 "general_operand"))]
"TARGET_EITHER"
"
+ gcc_checking_assert (!MEM_P (operands[0])
+ || MEM_ALIGN (operands[0])
+ >= GET_MODE_ALIGNMENT (HImode));
+ gcc_checking_assert (!MEM_P (operands[1])
+ || MEM_ALIGN (operands[1])
+ >= GET_MODE_ALIGNMENT (HImode));
if (TARGET_ARM)
{
if (can_create_pseudo_p ())
@@ -6898,6 +6916,12 @@
(match_operand:HF 1 "general_operand"))]
"TARGET_EITHER"
"
+ gcc_checking_assert (!MEM_P (operands[0])
+ || MEM_ALIGN (operands[0])
+ >= GET_MODE_ALIGNMENT (HFmode));
+ gcc_checking_assert (!MEM_P (operands[1])
+ || MEM_ALIGN (operands[1])
+ >= GET_MODE_ALIGNMENT (HFmode));
if (TARGET_32BIT)
{
if (MEM_P (operands[0]))
@@ -6962,6 +6986,12 @@
(match_operand:SF 1 "general_operand"))]
"TARGET_EITHER"
"
+ gcc_checking_assert (!MEM_P (operands[0])
+ || MEM_ALIGN (operands[0])
+ >= GET_MODE_ALIGNMENT (SFmode));
+ gcc_checking_assert (!MEM_P (operands[1])
+ || MEM_ALIGN (operands[1])
+ >= GET_MODE_ALIGNMENT (SFmode));
if (TARGET_32BIT)
{
if (MEM_P (operands[0]))
@@ -7057,6 +7087,12 @@
(match_operand:DF 1 "general_operand"))]
"TARGET_EITHER"
"
+ gcc_checking_assert (!MEM_P (operands[0])
+ || MEM_ALIGN (operands[0])
+ >= GET_MODE_ALIGNMENT (DFmode));
+ gcc_checking_assert (!MEM_P (operands[1])
+ || MEM_ALIGN (operands[1])
+ >= GET_MODE_ALIGNMENT (DFmode));
if (TARGET_32BIT)
{
if (MEM_P (operands[0]))
Index: gcc/config/arm/neon.md
===================================================================
--- gcc/config/arm/neon.md (revision 274168)
+++ gcc/config/arm/neon.md (working copy)
@@ -127,6 +127,12 @@
(match_operand:TI 1 "general_operand"))]
"TARGET_NEON"
{
+ gcc_checking_assert (!MEM_P (operands[0])
+ || MEM_ALIGN (operands[0])
+ >= GET_MODE_ALIGNMENT (TImode));
+ gcc_checking_assert (!MEM_P (operands[1])
+ || MEM_ALIGN (operands[1])
+ >= GET_MODE_ALIGNMENT (TImode));
if (can_create_pseudo_p ())
{
if (!REG_P (operands[0]))
@@ -139,6 +145,12 @@
(match_operand:VSTRUCT 1 "general_operand"))]
"TARGET_NEON"
{
+ gcc_checking_assert (!MEM_P (operands[0])
+ || MEM_ALIGN (operands[0])
+ >= GET_MODE_ALIGNMENT (<MODE>mode));
+ gcc_checking_assert (!MEM_P (operands[1])
+ || MEM_ALIGN (operands[1])
+ >= GET_MODE_ALIGNMENT (<MODE>mode));
if (can_create_pseudo_p ())
{
if (!REG_P (operands[0]))
@@ -151,6 +163,12 @@
(match_operand:VH 1 "s_register_operand"))]
"TARGET_NEON"
{
+ gcc_checking_assert (!MEM_P (operands[0])
+ || MEM_ALIGN (operands[0])
+ >= GET_MODE_ALIGNMENT (<MODE>mode));
+ gcc_checking_assert (!MEM_P (operands[1])
+ || MEM_ALIGN (operands[1])
+ >= GET_MODE_ALIGNMENT (<MODE>mode));
if (can_create_pseudo_p ())
{
if (!REG_P (operands[0]))
Index: gcc/config/arm/vec-common.md
===================================================================
--- gcc/config/arm/vec-common.md (revision 274168)
+++ gcc/config/arm/vec-common.md (working copy)
@@ -26,6 +26,12 @@
"TARGET_NEON
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
{
+ gcc_checking_assert (!MEM_P (operands[0])
+ || MEM_ALIGN (operands[0])
+ >= GET_MODE_ALIGNMENT (<MODE>mode));
+ gcc_checking_assert (!MEM_P (operands[1])
+ || MEM_ALIGN (operands[1])
+ >= GET_MODE_ALIGNMENT (<MODE>mode));
if (can_create_pseudo_p ())
{
if (!REG_P (operands[0]))
Index: gcc/expr.c
===================================================================
--- gcc/expr.c (revision 274168)
+++ gcc/expr.c (working copy)
@@ -10796,6 +10796,14 @@ expand_expr_real_1 (tree exp, rtx target, machine_
MEM_VOLATILE_P (op0) = 1;
}
+ if (MEM_P (op0) && TREE_CODE (tem) == FUNCTION_DECL)
+ {
+ if (op0 == orig_op0)
+ op0 = copy_rtx (op0);
+
+ set_mem_align (op0, BITS_PER_UNIT);
+ }
+
/* In cases where an aligned union has an unaligned object
as a field, we might be extracting a BLKmode value from
an integer-mode (e.g., SImode) object. Handle this case
Index: gcc/function.c
===================================================================
--- gcc/function.c (revision 274168)
+++ gcc/function.c (working copy)
@@ -2697,8 +2697,23 @@ assign_parm_find_stack_rtl (tree parm, struct assi
intentionally forcing upward padding. Otherwise we have to come
up with a guess at the alignment based on OFFSET_RTX. */
poly_int64 offset;
- if (data->locate.where_pad != PAD_DOWNWARD || data->entry_parm)
+ if (data->locate.where_pad == PAD_NONE || data->entry_parm)
align = boundary;
+ else if (data->locate.where_pad == PAD_UPWARD)
+ {
+ align = boundary;
+ /* If the argument offset is actually more aligned than the nominal
+ stack slot boundary, take advantage of that excess alignment.
+ Don't make any assumptions if STACK_POINTER_OFFSET is in use. */
+ if (poly_int_rtx_p (offset_rtx, &offset)
+ && STACK_POINTER_OFFSET == 0)
+ {
+ unsigned int offset_align = known_alignment (offset) * BITS_PER_UNIT;
+ if (offset_align == 0 || offset_align > STACK_BOUNDARY)
+ offset_align = STACK_BOUNDARY;
+ align = MAX (align, offset_align);
+ }
+ }
else if (poly_int_rtx_p (offset_rtx, &offset))
{
align = least_bit_hwi (boundary);
@@ -3127,6 +3142,7 @@ assign_parm_setup_reg (struct assign_parm_data_all
int unsignedp = TYPE_UNSIGNED (TREE_TYPE (parm));
bool did_conversion = false;
bool need_conversion, moved;
+ enum insn_code icode;
rtx rtl;
/* Store the parm in a pseudoregister during the function, but we may
@@ -3188,7 +3204,6 @@ assign_parm_setup_reg (struct assign_parm_data_all
conversion. We verify that this insn does not clobber any
hard registers. */
- enum insn_code icode;
rtx op0, op1;
icode = can_extend_p (promoted_nominal_mode, data->passed_mode,
@@ -3291,6 +3306,23 @@ assign_parm_setup_reg (struct assign_parm_data_all
did_conversion = true;
}
+ else if (MEM_P (data->entry_parm)
+ && GET_MODE_ALIGNMENT (promoted_nominal_mode)
+ > MEM_ALIGN (data->entry_parm)
+ && (((icode = optab_handler (movmisalign_optab,
+ promoted_nominal_mode))
+ != CODE_FOR_nothing)
+ || targetm.slow_unaligned_access (promoted_nominal_mode,
+ MEM_ALIGN (data->entry_parm))))
+ {
+ if (icode != CODE_FOR_nothing)
+ emit_insn (GEN_FCN (icode) (parmreg, validated_mem));
+ else
+ rtl = parmreg = extract_bit_field (validated_mem,
+ GET_MODE_BITSIZE (promoted_nominal_mode), 0,
+ unsignedp, parmreg,
+ promoted_nominal_mode, VOIDmode, false, NULL);
+ }
else
emit_move_insn (parmreg, validated_mem);
@@ -3449,11 +3481,17 @@ assign_parm_setup_stack (struct assign_parm_data_a
int align = STACK_SLOT_ALIGNMENT (data->passed_type,
GET_MODE (data->entry_parm),
TYPE_ALIGN (data->passed_type));
+ if (align < (int)GET_MODE_ALIGNMENT (GET_MODE (data->entry_parm))
+ && targetm.slow_unaligned_access (GET_MODE (data->entry_parm),
+ align))
+ align = GET_MODE_ALIGNMENT (GET_MODE (data->entry_parm));
data->stack_parm
= assign_stack_local (GET_MODE (data->entry_parm),
GET_MODE_SIZE (GET_MODE (data->entry_parm)),
align);
+ align = MEM_ALIGN (data->stack_parm);
set_mem_attributes (data->stack_parm, parm, 1);
+ set_mem_align (data->stack_parm, align);
}
dest = validize_mem (copy_rtx (data->stack_parm));
Index: gcc/testsuite/gcc.target/arm/unaligned-argument-1.c
===================================================================
--- gcc/testsuite/gcc.target/arm/unaligned-argument-1.c (revision 0)
+++ gcc/testsuite/gcc.target/arm/unaligned-argument-1.c (working copy)
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arm_ok } */
+/* { dg-require-effective-target arm_ldrd_strd_ok } */
+/* { dg-options "-marm -mno-unaligned-access -O3" } */
+
+struct s {
+ int a, b;
+} __attribute__((aligned(8)));
+
+struct s f0;
+
+void f(int a, int b, int c, int d, struct s f)
+{
+ f0 = f;
+}
+
+/* { dg-final { scan-assembler-times "ldrd" 1 } } */
+/* { dg-final { scan-assembler-times "strd" 1 } } */
+/* { dg-final { scan-assembler-times "stm" 0 } } */
Index: gcc/testsuite/gcc.target/arm/unaligned-argument-2.c
===================================================================
--- gcc/testsuite/gcc.target/arm/unaligned-argument-2.c (revision 0)
+++ gcc/testsuite/gcc.target/arm/unaligned-argument-2.c (working copy)
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arm_ok } */
+/* { dg-require-effective-target arm_ldrd_strd_ok } */
+/* { dg-options "-marm -mno-unaligned-access -O3" } */
+
+struct s {
+ int a, b;
+} __attribute__((aligned(8)));
+
+struct s f0;
+
+void f(int a, int b, int c, int d, int e, struct s f)
+{
+ f0 = f;
+}
+
+/* { dg-final { scan-assembler-times "ldrd" 0 } } */
+/* { dg-final { scan-assembler-times "strd" 0 } } */
+/* { dg-final { scan-assembler-times "stm" 1 } } */
Index: gcc/varasm.c
===================================================================
--- gcc/varasm.c (revision 274168)
+++ gcc/varasm.c (working copy)
@@ -1085,6 +1085,10 @@ align_variable (tree decl, bool dont_output_data)
}
}
+ if (align < GET_MODE_ALIGNMENT (DECL_MODE (decl))
+ && targetm.slow_unaligned_access (DECL_MODE (decl), align))
+ align = GET_MODE_ALIGNMENT (DECL_MODE (decl));
+
/* Reset the alignment in case we have made it tighter, so we can benefit
from it in get_pointer_alignment. */
SET_DECL_ALIGN (decl, align);
next prev parent reply other threads:[~2019-08-08 14:11 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-10 12:51 [PATCHv2] " Bernd Edlinger
2019-03-19 14:01 ` [PING] " Bernd Edlinger
2019-03-21 11:26 ` Richard Biener
2019-03-22 17:47 ` Bernd Edlinger
2019-03-25 9:28 ` Richard Biener
2019-07-30 22:13 ` [PATCHv3] " Bernd Edlinger
2019-07-31 13:17 ` Richard Earnshaw (lists)
2019-08-01 11:19 ` Bernd Edlinger
2019-08-02 9:10 ` Richard Earnshaw (lists)
2019-08-02 13:11 ` Richard Biener
2019-08-02 19:01 ` Bernd Edlinger
2019-08-08 14:20 ` Bernd Edlinger [this message]
2019-08-14 10:54 ` [PING] [PATCHv4] " Bernd Edlinger
2019-08-14 12:27 ` Richard Biener
2019-08-14 22:26 ` Bernd Edlinger
2019-08-15 8:58 ` Richard Biener
2019-08-15 12:38 ` Bernd Edlinger
2019-08-15 13:03 ` Richard Biener
2019-08-15 14:33 ` Richard Biener
2019-08-15 15:28 ` Bernd Edlinger
2019-08-15 17:42 ` Richard Biener
2019-08-15 21:19 ` [PATCHv5] " Bernd Edlinger
2019-08-20 5:38 ` Jeff Law
2019-08-20 15:04 ` John David Anglin
[not found] ` <0d39b64f-67d9-7857-cf4e-36f09c0dc15e@bell.net>
2019-08-20 16:03 ` Fwd: " Bernd Edlinger
2019-09-04 12:53 ` Richard Earnshaw (lists)
2019-09-04 13:29 ` Bernd Edlinger
2019-09-04 14:14 ` Richard Earnshaw (lists)
2019-09-04 15:00 ` Bernd Edlinger
2019-09-04 15:48 ` Richard Earnshaw (lists)
2019-09-05 9:21 ` Richard Earnshaw (lists)
2019-09-05 9:35 ` Bernd Edlinger
2019-09-06 10:15 ` Bernd Edlinger
2019-09-06 10:18 ` Richard Earnshaw (lists)
2019-08-15 21:27 ` [PATCH] Sanitizing the middle-end interface to the back-end for strict alignment Bernd Edlinger
2019-08-17 10:11 ` Bernd Edlinger
2019-08-23 0:01 ` Jeff Law
2019-08-23 0:05 ` Jeff Law
2019-08-23 15:15 ` [PING] " Bernd Edlinger
2019-08-27 10:07 ` Kyrill Tkachov
2019-08-28 11:50 ` Bernd Edlinger
2019-08-28 12:01 ` Kyrill Tkachov
2019-08-28 13:54 ` Christophe Lyon
2019-08-28 21:48 ` Bernd Edlinger
2019-08-29 9:09 ` Kyrill Tkachov
2019-08-29 10:00 ` Christophe Lyon
2019-08-29 22:57 ` Bernd Edlinger
2019-08-30 10:07 ` Kyrill Tkachov
2019-08-30 15:22 ` Christophe Lyon
2019-08-14 11:56 ` [PATCHv3] Fix not 8-byte aligned ldrd/strd on ARMv5 (PR 89544) Richard Biener
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