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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi,=0A= =0A= Changes suggested here and those discussed off-list have been=0A= implemented in V2 of the patch.=0A= =0A= Regression tested and bootstrapped on aarch64-none-linux-gnu - no=0A= issues.=0A= =0A= Ok for master?=0A= =0A= Thanks,=0A= Jonathan=0A= =0A= ---=0A= =0A= gcc/ChangeLog:=0A= =0A= 2021-07-19 Jonathan Wright =0A= =0A= * config/aarch64/aarch64.c (aarch64_strip_extend_vec_half):=0A= Define.=0A= (aarch64_rtx_mult_cost): Traverse RTL tree to prevent cost of=0A= vec_select high-half from being added into Neon multiply=0A= cost.=0A= * rtlanal.c (vec_series_highpart_p): Define.=0A= * rtlanal.h (vec_series_highpart_p): Declare.=0A= =0A= gcc/testsuite/ChangeLog:=0A= =0A= * gcc.target/aarch64/vmul_high_cost.c: New test.=0A= =0A= From: Richard Sandiford =0A= Sent: 04 August 2021 10:05=0A= To: Jonathan Wright via Gcc-patches =0A= Cc: Jonathan Wright =0A= Subject: Re: [PATCH] aarch64: Don't include vec_select high-half in SIMD mu= ltiply cost =0A= =A0=0A= Jonathan Wright via Gcc-patches writes:=0A= > Hi,=0A= >=0A= > The Neon multiply/multiply-accumulate/multiply-subtract instructions=0A= > can select the top or bottom half of the operand registers. This=0A= > selection does not change the cost of the underlying instruction and=0A= > this should be reflected by the RTL cost function.=0A= >=0A= > This patch adds RTL tree traversal in the Neon multiply cost function=0A= > to match vec_select high-half of its operands. This traversal=0A= > prevents the cost of the vec_select from being added into the cost of=0A= > the multiply - meaning that these instructions can now be emitted in=0A= > the combine pass as they are no longer deemed prohibitively=0A= > expensive.=0A= >=0A= > Regression tested and bootstrapped on aarch64-none-linux-gnu - no=0A= > issues.=0A= =0A= Like you say, the instructions can handle both the low and high halves.=0A= Shouldn't we also check for the low part (as a SIGN/ZERO_EXTEND of=0A= a subreg)?=0A= =0A= > Ok for master?=0A= >=0A= > Thanks,=0A= > Jonathan=0A= >=0A= > ---=0A= >=0A= > gcc/ChangeLog:=0A= >=0A= > 2021-07-19 =A0Jonathan Wright =A0=0A= >=0A= >=A0=A0=A0=A0=A0=A0=A0 * config/aarch64/aarch64.c (aarch64_vec_select_high_= operand_p):=0A= >=A0=A0=A0=A0=A0=A0=A0 Define.=0A= >=A0=A0=A0=A0=A0=A0=A0 (aarch64_rtx_mult_cost): Traverse RTL tree to preven= t cost of=0A= >=A0=A0=A0=A0=A0=A0=A0 vec_select high-half from being added into Neon mult= iply=0A= >=A0=A0=A0=A0=A0=A0=A0 cost.=0A= >=A0=A0=A0=A0=A0=A0=A0 * rtlanal.c (vec_series_highpart_p): Define.=0A= >=A0=A0=A0=A0=A0=A0=A0 * rtlanal.h (vec_series_highpart_p): Declare.=0A= >=0A= > gcc/testsuite/ChangeLog:=0A= >=0A= >=A0=A0=A0=A0=A0=A0=A0 * gcc.target/aarch64/vmul_high_cost.c: New test.=0A= >=0A= > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c= =0A= > index 5809887997305317c5a81421089db431685e2927..a49672afe785e3517250d3244= 68edacceab5c9d3 100644=0A= > --- a/gcc/config/aarch64/aarch64.c=0A= > +++ b/gcc/config/aarch64/aarch64.c=0A= > @@ -76,6 +76,7 @@=0A= >=A0 #include "function-abi.h"=0A= >=A0 #include "gimple-pretty-print.h"=0A= >=A0 #include "tree-ssa-loop-niter.h"=0A= > +#include "rtlanal.h"=0A= >=A0 =0A= >=A0 /* This file should be included last.=A0 */=0A= >=A0 #include "target-def.h"=0A= > @@ -11970,6 +11971,19 @@ aarch64_cheap_mult_shift_p (rtx x)=0A= >=A0=A0=A0 return false;=0A= >=A0 }=0A= >=A0 =0A= > +/* Return true iff X is an operand of a select-high-half vector=0A= > +=A0=A0 instruction.=A0 */=0A= > +=0A= > +static bool=0A= > +aarch64_vec_select_high_operand_p (rtx x)=0A= > +{=0A= > +=A0 return ((GET_CODE (x) =3D=3D ZERO_EXTEND || GET_CODE (x) =3D=3D SIGN= _EXTEND)=0A= > +=A0=A0=A0=A0=A0=A0 && GET_CODE (XEXP (x, 0)) =3D=3D VEC_SELECT=0A= > +=A0=A0=A0=A0=A0=A0 && vec_series_highpart_p (GET_MODE (XEXP (x, 0)),=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0 GET_MODE (XEXP (XEXP (x, 0), 0)),=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0 XEXP (XEXP (x, 0), 1)));=0A= > +}=0A= > +=0A= >=A0 /* Helper function for rtx cost calculation.=A0 Calculate the cost of= =0A= >=A0=A0=A0=A0 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS = rtx.=0A= >=A0=A0=A0=A0 Return the calculated cost of the expression, recursing manua= lly in to=0A= > @@ -11995,6 +12009,13 @@ aarch64_rtx_mult_cost (rtx x, enum rtx_code code= , int outer, bool speed)=0A= >=A0=A0=A0=A0=A0=A0=A0 unsigned int vec_flags =3D aarch64_classify_vector_m= ode (mode);=0A= >=A0=A0=A0=A0=A0=A0=A0 if (vec_flags & VEC_ADVSIMD)=0A= >=A0=A0=A0=A0=A0=A0=A0 {=0A= > +=A0=A0=A0=A0=A0=A0 /* The select-operand-high-half versions of the instr= uction have the=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0 same cost as the three vector version - don'= t add the costs of the=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0 select into the costs of the multiply.=A0 */= =0A= > +=A0=A0=A0=A0=A0=A0 if (aarch64_vec_select_high_operand_p (op0))=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0 op0 =3D XEXP (XEXP (op0, 0), 0);=0A= > +=A0=A0=A0=A0=A0=A0 if (aarch64_vec_select_high_operand_p (op1))=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0 op1 =3D XEXP (XEXP (op1, 0), 0);=0A= =0A= For consistency with aarch64_strip_duplicate_vec_elt, I think this=0A= should be something like aarch64_strip_vec_extension, returning=0A= the inner rtx on success and the original one on failure.=0A= =0A= Thanks,=0A= Richard=0A= =0A= >=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* The by-element versions of the instruction = have the same costs as=0A= >=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 the normal 3-vector version.=A0 So do= n't add the costs of the=0A= >=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 duplicate or subsequent select into t= he costs of the multiply.=A0 We=0A= > diff --git a/gcc/rtlanal.h b/gcc/rtlanal.h=0A= > index e1642424db89736675ac3e0d505aeaa59dca8bad..542dc7898bead27d3da89e513= 8c49563ba226eae 100644=0A= > --- a/gcc/rtlanal.h=0A= > +++ b/gcc/rtlanal.h=0A= > @@ -331,6 +331,10 @@ inline vec_rtx_properties_base::~vec_rtx_properties_= base ()=0A= >=A0=A0=A0=A0 collecting the references a second time.=A0 */=0A= >=A0 using vec_rtx_properties =3D growing_rtx_properties;=0A= >=A0 =0A= > +bool=0A= > +vec_series_highpart_p (machine_mode result_mode, machine_mode op_mode,= =0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 rtx sel);=0A= > +=0A= >=A0 bool=0A= >=A0 vec_series_lowpart_p (machine_mode result_mode, machine_mode op_mode, = rtx sel);=0A= >=A0 =0A= > diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c=0A= > index ec7a062829cb4ead3eaedf1546956107f4ad3bb2..3db49e7a8237bef8ffd9aa403= 6bb2cfdb1cee6d5 100644=0A= > --- a/gcc/rtlanal.c=0A= > +++ b/gcc/rtlanal.c=0A= > @@ -6941,6 +6941,25 @@ register_asm_p (const_rtx x)=0A= >=A0=A0=A0=A0=A0=A0=A0=A0=A0 && DECL_REGISTER (REG_EXPR (x)));=0A= >=A0 }=0A= >=A0 =0A= > +/* Return true if, for all OP of mode OP_MODE:=0A= > +=0A= > +=A0=A0=A0=A0 (vec_select:RESULT_MODE OP SEL)=0A= > +=0A= > +=A0=A0 is equivalent to the highpart RESULT_MODE of OP.=A0 */=0A= > +=0A= > +bool=0A= > +vec_series_highpart_p (machine_mode result_mode, machine_mode op_mode, r= tx sel)=0A= > +{=0A= > +=A0 int nunits;=0A= > +=A0 if (GET_MODE_NUNITS (op_mode).is_constant (&nunits)=0A= > +=A0=A0=A0=A0=A0 && targetm.can_change_mode_class (op_mode, result_mode, = ALL_REGS))=0A= > +=A0=A0=A0 {=0A= > +=A0=A0=A0=A0=A0 int offset =3D BYTES_BIG_ENDIAN ? 0 : nunits - XVECLEN (= sel, 0);=0A= > +=A0=A0=A0=A0=A0 return rtvec_series_p (XVEC (sel, 0), offset);=0A= > +=A0=A0=A0 }=0A= > +=A0 return false;=0A= > +}=0A= > +=0A= >=A0 /* Return true if, for all OP of mode OP_MODE:=0A= >=A0 =0A= >=A0=A0=A0=A0=A0=A0 (vec_select:RESULT_MODE OP SEL)=0A= > diff --git a/gcc/testsuite/gcc.target/aarch64/vmul_high_cost.c b/gcc/test= suite/gcc.target/aarch64/vmul_high_cost.c=0A= > new file mode 100644=0A= > index 0000000000000000000000000000000000000000..ecc02e652a4ba40e2fd68154c= a8be5d322f43468=0A= > --- /dev/null=0A= > +++ b/gcc/testsuite/gcc.target/aarch64/vmul_high_cost.c=0A= > @@ -0,0 +1,85 @@=0A= > +/* { dg-do compile } */=0A= > +/* { dg-options "-O3" } */=0A= > +=0A= > +#include =0A= > +=0A= > +#define TEST_MULL_VEC(name, rettype, intype, ts, rs) \=0A= > +=A0 rettype test_ ## name ## _ ## ts (intype a, intype b, intype c) \=0A= > +=A0=A0=A0=A0 { \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 rettype t0 =3D name ## _ ## ts (vge= t_high_ ## ts (a), \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 vget_high_ ## ts (c)= ); \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 rettype t1 =3D name ## _ ## ts (vge= t_high_ ## ts (b), \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 vget_high_ ## ts (c)= ); \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return vqaddq ## _ ## rs (t0, t1); = \=0A= > +=A0=A0=A0=A0 }=0A= > +=0A= > +TEST_MULL_VEC (vmull, int16x8_t, int8x16_t, s8, s16)=0A= > +TEST_MULL_VEC (vmull, uint16x8_t, uint8x16_t, u8, u16)=0A= > +TEST_MULL_VEC (vmull, int32x4_t, int16x8_t, s16, s32)=0A= > +TEST_MULL_VEC (vmull, uint32x4_t, uint16x8_t, u16, u32)=0A= > +TEST_MULL_VEC (vmull, int64x2_t, int32x4_t, s32, s64)=0A= > +TEST_MULL_VEC (vmull, uint64x2_t, uint32x4_t, u32, u64)=0A= > +=0A= > +TEST_MULL_VEC (vqdmull, int32x4_t, int16x8_t, s16, s32)=0A= > +TEST_MULL_VEC (vqdmull, int64x2_t, int32x4_t, s32, s64)=0A= > +=0A= > +#define TEST_MULL_N(name, rettype, intype, ts, rs) \=0A= > +=A0 rettype test_ ## name ## _ ## ts (intype a, intype b, intype c) \=0A= > +=A0=A0=A0=A0 { \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 rettype t0 =3D name ## _ ## ts (vge= t_high_ ## ts (a), b[1]); \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 rettype t1 =3D name ## _ ## ts (vge= t_high_ ## ts (a), c[1]); \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return vqaddq ## _ ## rs (t0, t1); = \=0A= > +=A0=A0=A0=A0 }=0A= > +=0A= > +TEST_MULL_N (vmull_n, int32x4_t, int16x8_t, s16, s32)=0A= > +TEST_MULL_N (vmull_n, uint32x4_t, uint16x8_t, u16, u32)=0A= > +TEST_MULL_N (vmull_n, int64x2_t, int32x4_t, s32, s64)=0A= > +TEST_MULL_N (vmull_n, uint64x2_t, uint32x4_t, u32, u64)=0A= > +=0A= > +TEST_MULL_N (vqdmull_n, int32x4_t, int16x8_t, s16, s32)=0A= > +TEST_MULL_N (vqdmull_n, int64x2_t, int32x4_t, s32, s64)=0A= > +=0A= > +#define TEST_MLXL_VEC(name, rettype, intype, ts) \=0A= > +=A0 rettype test_ ## name ## _ ## ts (rettype acc, intype a, intype b, \= =0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0 intype c) \=0A= > +=A0=A0=A0=A0 { \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 acc =3D name ## _ ## ts (acc, vget_= high_ ## ts (a), \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 vget_high_ ## ts (b)); \= =0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return name ## _ ## ts (acc, vget_h= igh_ ## ts (a), \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 vget_high_ ## ts (c)); = \=0A= > +=A0=A0=A0=A0 }=0A= > +=0A= > +TEST_MLXL_VEC (vmlal, int16x8_t, int8x16_t, s8)=0A= > +TEST_MLXL_VEC (vmlal, uint16x8_t, uint8x16_t, u8)=0A= > +TEST_MLXL_VEC (vmlal, int32x4_t, int16x8_t, s16)=0A= > +TEST_MLXL_VEC (vmlal, uint32x4_t, uint16x8_t, u16)=0A= > +=0A= > +TEST_MLXL_VEC (vmlsl, int16x8_t, int8x16_t, s8)=0A= > +TEST_MLXL_VEC (vmlsl, uint16x8_t, uint8x16_t, u8)=0A= > +TEST_MLXL_VEC (vmlsl, int32x4_t, int16x8_t, s16)=0A= > +TEST_MLXL_VEC (vmlsl, uint32x4_t, uint16x8_t, u16)=0A= > +=0A= > +#define TEST_MLXL_N(name, rettype, intype, ts) \=0A= > +=A0 rettype test_ ## name ## _ ## ts (rettype acc, intype a, intype b) \= =0A= > +=A0=A0=A0=A0 { \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 acc =3D name ## _ ## ts (acc, vget_= high_ ## ts (a), b[1]); \=0A= > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return name ## _ ## ts (acc, vget_h= igh_ ## ts (a), b[1]); \=0A= > +=A0=A0=A0=A0 }=0A= > +=0A= > +TEST_MLXL_N (vmlal_n, int32x4_t, int16x8_t, s16)=0A= > +TEST_MLXL_N (vmlal_n, uint32x4_t, uint16x8_t, u16)=0A= > +TEST_MLXL_N (vmlal_n, int64x2_t, int32x4_t, s32)=0A= > +TEST_MLXL_N (vmlal_n, uint64x2_t, uint32x4_t, u32)=0A= > +=0A= > +TEST_MLXL_N (vmlsl_n, int32x4_t, int16x8_t, s16)=0A= > +TEST_MLXL_N (vmlsl_n, uint32x4_t, uint16x8_t, u16)=0A= > +TEST_MLXL_N (vmlsl_n, int64x2_t, int32x4_t, s32)=0A= > +TEST_MLXL_N (vmlsl_n, uint64x2_t, uint32x4_t, u32)=0A= > +=0A= > +TEST_MLXL_N (vqdmlal_n, int32x4_t, int16x8_t, s16)=0A= > +TEST_MLXL_N (vqdmlal_n, int64x2_t, int32x4_t, s32)=0A= > +=0A= > +TEST_MLXL_N (vqdmlsl_n, int32x4_t, int16x8_t, s16)=0A= > +TEST_MLXL_N (vqdmlsl_n, int64x2_t, int32x4_t, s32)=0A= > +=0A= > +/* { dg-final { scan-assembler-not "dup\\t" } } */= --_002_DB9PR08MB69598114B713B528D8ACB39DEBF19DB9PR08MB6959eurp_ Content-Type: application/octet-stream; name="rb14704.patch" Content-Description: rb14704.patch Content-Disposition: attachment; filename="rb14704.patch"; size=6977; creation-date="Wed, 04 Aug 2021 15:27:01 GMT"; modification-date="Wed, 04 Aug 2021 15:27:01 GMT" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0LmMgYi9nY2MvY29uZmlnL2Fh cmNoNjQvYWFyY2g2NC5jCmluZGV4IDBlYWU5MjViZTA3NzIyZTJkODBjMDZiMWVlYWZiNTYxMWJh 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