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From: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
To: "Pop, Sebastian" <spop@amazon.com>,
	"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE
Date: Tue, 19 Apr 2022 12:51:13 +0000	[thread overview]
Message-ID: <DB9PR08MB755949D95EC2887AA7B54EA983F29@DB9PR08MB7559.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <1650306160027.35616@amazon.com>

Hi Sebastian,

> Wilco pointed out in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105162#c7​ that
> "Only __sync needs the extra full barrier, but __atomic does not."
> The attached patch does that by adding out-of-line functions for MEMMODEL_SYNC_*.
> Those new functions contain a barrier on the path without LSE instructions.

Yes, adding _sync versions of the outline functions is the correct approach. However
there is no need to have separate _acq/_rel/_seq variants for every function since all
but one are _seq. Also we should ensure we generate the same sequence as the inlined
versions so that they are consistent. This means ensuring the LDXR macro ignores the
'A' for the _sync variants and the swp function switches to acquire semantics.

Cheers,
Wilco

  reply	other threads:[~2022-04-19 12:51 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-07 20:15 Pop, Sebastian
2022-04-18 18:22 ` Pop, Sebastian
2022-04-19 12:51   ` Wilco Dijkstra [this message]
2022-04-25 22:06     ` Pop, Sebastian
2022-05-03 15:33       ` Wilco Dijkstra
2022-05-04 14:23         ` Pop, Sebastian
2022-05-13 14:58           ` Richard Sandiford
2022-05-13 15:41             ` Wilco Dijkstra
2022-05-13 20:32               ` Pop, Sebastian
2022-05-16 11:42                 ` Richard Sandiford

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