From: Jonathan Wright <Jonathan.Wright@arm.com>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: [PATCH] testsuite: aarch64: Add zero-high-half tests for narrowing shifts
Date: Wed, 16 Jun 2021 08:53:49 +0000 [thread overview]
Message-ID: <DBBPR08MB4758E6633D60225CB2B9D5B1EB0F9@DBBPR08MB4758.eurprd08.prod.outlook.com> (raw)
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Hi,
This patch adds tests to verify that Neon narrowing-shift instructions
clear the top half of the result vector. It is sufficient to show that a
subsequent combine with a zero-vector is optimized away - leaving
just the narrowing-shift instruction.
Ok for master?
Thanks,
Jonathan
---
gcc/testsuite/ChangeLog:
2021-06-15 Jonathan Wright <jonathan.wright@arm.com>
* gcc.target/aarch64/narrow_zero_high_half.c: New test.
[-- Attachment #2: rb14569.patch --]
[-- Type: application/octet-stream, Size: 2916 bytes --]
diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_zero_high_half.c b/gcc/testsuite/gcc.target/aarch64/narrow_zero_high_half.c
new file mode 100644
index 0000000000000000000000000000000000000000..27fa0e640ab2b37781376c40ce4ca37602c72393
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/narrow_zero_high_half.c
@@ -0,0 +1,60 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include <arm_neon.h>
+
+#define TEST_SHIFT(name, rettype, intype, fs, rs) \
+ rettype test_ ## name ## _ ## fs ## _zero_high \
+ (intype a) \
+ { \
+ return vcombine_ ## rs (name ## _ ## fs (a, 4), \
+ vdup_n_ ## rs (0)); \
+ }
+
+TEST_SHIFT (vshrn_n, int8x16_t, int16x8_t, s16, s8)
+TEST_SHIFT (vshrn_n, int16x8_t, int32x4_t, s32, s16)
+TEST_SHIFT (vshrn_n, int32x4_t, int64x2_t, s64, s32)
+TEST_SHIFT (vshrn_n, uint8x16_t, uint16x8_t, u16, u8)
+TEST_SHIFT (vshrn_n, uint16x8_t, uint32x4_t, u32, u16)
+TEST_SHIFT (vshrn_n, uint32x4_t, uint64x2_t, u64, u32)
+
+TEST_SHIFT (vrshrn_n, int8x16_t, int16x8_t, s16, s8)
+TEST_SHIFT (vrshrn_n, int16x8_t, int32x4_t, s32, s16)
+TEST_SHIFT (vrshrn_n, int32x4_t, int64x2_t, s64, s32)
+TEST_SHIFT (vrshrn_n, uint8x16_t, uint16x8_t, u16, u8)
+TEST_SHIFT (vrshrn_n, uint16x8_t, uint32x4_t, u32, u16)
+TEST_SHIFT (vrshrn_n, uint32x4_t, uint64x2_t, u64, u32)
+
+TEST_SHIFT (vqshrn_n, int8x16_t, int16x8_t, s16, s8)
+TEST_SHIFT (vqshrn_n, int16x8_t, int32x4_t, s32, s16)
+TEST_SHIFT (vqshrn_n, int32x4_t, int64x2_t, s64, s32)
+TEST_SHIFT (vqshrn_n, uint8x16_t, uint16x8_t, u16, u8)
+TEST_SHIFT (vqshrn_n, uint16x8_t, uint32x4_t, u32, u16)
+TEST_SHIFT (vqshrn_n, uint32x4_t, uint64x2_t, u64, u32)
+
+TEST_SHIFT (vqrshrn_n, int8x16_t, int16x8_t, s16, s8)
+TEST_SHIFT (vqrshrn_n, int16x8_t, int32x4_t, s32, s16)
+TEST_SHIFT (vqrshrn_n, int32x4_t, int64x2_t, s64, s32)
+TEST_SHIFT (vqrshrn_n, uint8x16_t, uint16x8_t, u16, u8)
+TEST_SHIFT (vqrshrn_n, uint16x8_t, uint32x4_t, u32, u16)
+TEST_SHIFT (vqrshrn_n, uint32x4_t, uint64x2_t, u64, u32)
+
+TEST_SHIFT (vqshrun_n, uint8x16_t, int16x8_t, s16, u8)
+TEST_SHIFT (vqshrun_n, uint16x8_t, int32x4_t, s32, u16)
+TEST_SHIFT (vqshrun_n, uint32x4_t, int64x2_t, s64, u32)
+
+TEST_SHIFT (vqrshrun_n, uint8x16_t, int16x8_t, s16, u8)
+TEST_SHIFT (vqrshrun_n, uint16x8_t, int32x4_t, s32, u16)
+TEST_SHIFT (vqrshrun_n, uint32x4_t, int64x2_t, s64, u32)
+
+/* { dg-final { scan-assembler-not "dup\\t" } } */
+
+/* { dg-final { scan-assembler-times "\\trshrn\\tv" 6} } */
+/* { dg-final { scan-assembler-times "\\tshrn\\tv" 6} } */
+/* { dg-final { scan-assembler-times "\\tsqshrun\\tv" 3} } */
+/* { dg-final { scan-assembler-times "\\tsqrshrun\\tv" 3} } */
+/* { dg-final { scan-assembler-times "\\tsqshrn\\tv" 3} } */
+/* { dg-final { scan-assembler-times "\\tuqshrn\\tv" 3} } */
+/* { dg-final { scan-assembler-times "\\tsqrshrn\\tv" 3} } */
+/* { dg-final { scan-assembler-times "\\tuqrshrn\\tv" 3} } */
next reply other threads:[~2021-06-16 8:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-16 8:53 Jonathan Wright [this message]
2021-06-16 12:38 ` Richard Sandiford
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