From: Jonathan Wright <Jonathan.Wright@arm.com>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: [PATCH 16/20] aarch64: Relax aarch64_<sur><addsub>hn2<mode> RTL pattern
Date: Wed, 28 Apr 2021 14:53:34 +0000 [thread overview]
Message-ID: <DBBPR08MB4758EA3D5E82073F97309CE4EB409@DBBPR08MB4758.eurprd08.prod.outlook.com> (raw)
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Hi,
As subject, this patch implements the v[r]addhn2 and v[r]subhn2 Neon
intrinsic RTL patterns using a vec_concat of a register_operand and an
ADDSUBHN unspec - instead of just an ADDSUBHN2 unspec. This more
relaxed pattern allows for more aggressive combinations and ultimately
better code generation.
Regression tested and bootstrapped on aarch64-none-linux-gnu and
aarch64_be-none-elf - no issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
2021-03-03 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn2<mode>):
Implement as an expand emitting a big/little endian
instruction pattern.
(aarch64_<sur><addsub>hn2<mode>_insn_le): Define.
(aarch64_<sur><addsub>hn2<mode>_insn_be): Define.
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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index fa4972e769ee79dfd369223e867ed18beb6dfb2c..4da5711eaedeb77da1bbeab49af637a7fafea9c2 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4652,17 +4652,48 @@
[(set_attr "type" "neon_<addsub>_halve_narrow_q")]
)
-(define_insn "aarch64_<sur><addsub>hn2<mode>"
+(define_insn "aarch64_<sur><addsub>hn2<mode>_insn_le"
[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
- (unspec:<VNARROWQ2> [(match_operand:<VNARROWQ> 1 "register_operand" "0")
- (match_operand:VQN 2 "register_operand" "w")
- (match_operand:VQN 3 "register_operand" "w")]
- ADDSUBHN2))]
- "TARGET_SIMD"
+ (vec_concat:<VNARROWQ2>
+ (match_operand:<VNARROWQ> 1 "register_operand" "0")
+ (unspec:<VNARROWQ> [(match_operand:VQN 2 "register_operand" "w")
+ (match_operand:VQN 3 "register_operand" "w")]
+ ADDSUBHN)))]
+ "TARGET_SIMD && !BYTES_BIG_ENDIAN"
"<sur><addsub>hn2\\t%0.<V2ntype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "type" "neon_<addsub>_halve_narrow_q")]
)
+(define_insn "aarch64_<sur><addsub>hn2<mode>_insn_be"
+ [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
+ (vec_concat:<VNARROWQ2>
+ (unspec:<VNARROWQ> [(match_operand:VQN 2 "register_operand" "w")
+ (match_operand:VQN 3 "register_operand" "w")]
+ ADDSUBHN)
+ (match_operand:<VNARROWQ> 1 "register_operand" "0")))]
+ "TARGET_SIMD && BYTES_BIG_ENDIAN"
+ "<sur><addsub>hn2\\t%0.<V2ntype>, %2.<Vtype>, %3.<Vtype>"
+ [(set_attr "type" "neon_<addsub>_halve_narrow_q")]
+)
+
+(define_expand "aarch64_<sur><addsub>hn2<mode>"
+ [(match_operand:<VNARROWQ2> 0 "register_operand")
+ (unspec:<VNARROWQ2> [(match_operand:<VNARROWQ> 1 "register_operand")
+ (match_operand:VQN 2 "register_operand")
+ (match_operand:VQN 3 "register_operand")]
+ ADDSUBHN2)]
+ "TARGET_SIMD"
+ {
+ if (BYTES_BIG_ENDIAN)
+ emit_insn (gen_aarch64_<sur><addsub>hn2<mode>_insn_be (operands[0],
+ operands[1], operands[2], operands[3]));
+ else
+ emit_insn (gen_aarch64_<sur><addsub>hn2<mode>_insn_le (operands[0],
+ operands[1], operands[2], operands[3]));
+ DONE;
+ }
+)
+
;; pmul.
(define_insn "aarch64_pmul<mode>"
next reply other threads:[~2021-04-28 14:53 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-28 14:53 Jonathan Wright [this message]
2021-04-28 15:57 ` Richard Sandiford
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