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Thu, 14 Nov 2019 19:14:02 +0000 From: Srinath Parvathaneni To: "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov Subject: [PATCH][ARM][GCC][11x]: MVE ACLE vector interleaving store and deinterleaving load intrinsics and also aliases to vstr and vldr intrinsics. Date: Thu, 14 Nov 2019 19:16:00 -0000 Message-ID: References: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> In-Reply-To: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-PUrlCount: 1 x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:2733;OLM:2733; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(396003)(366004)(376002)(346002)(136003)(54534003)(199004)(189003)(81156014)(316002)(81166006)(30864003)(2501003)(44832011)(4326008)(74316002)(7696005)(99286004)(478600001)(186003)(11346002)(26005)(54906003)(76176011)(52536014)(5660300002)(446003)(25786009)(71190400001)(71200400001)(33656002)(66946007)(52116002)(305945005)(66556008)(7736002)(66446008)(6666004)(66476007)(66616009)(64756008)(256004)(5024004)(9686003)(966005)(5640700003)(3846002)(66066001)(6916009)(86362001)(486006)(6506007)(6436002)(14454004)(8936002)(2906002)(6116002)(2351001)(55016002)(8676002)(102836004)(386003)(476003)(6306002)(579004)(559001)(569006);DIR:OUT;SFP:1101;SCL:1;SRVR:DBBPR08MB4807;H:DBBPR08MB4775.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: MK3BT4caFK0URSwnAMUkAnhxfKgzlFsYdtt1MWHs+xNW55Mic6WMON9NdpchAzZ5Ds8s7x1HDyLQ6ecJYCASYvlkUb4JzuAPs9EK5CEaExoGeiTuFn0Kfn7A6VlWQqxsU6EfrnSliDf0yUfBPPnfbmO09uEZrUQjdn4tmUXgMHL0lBVadNdr2dpQkcB4nRi0rT8xuYRzwdmr55beMnixUmd+TEDCRXA28kvjhn0rrqxDfFMuimPU2tlFlfa7deiPaRHQ4Z+TsHl21YDaiN6tLSU5lTyWKqeJqW+w4P/g3Ny0gRUQta67R3/NSa5tP7NUt4uqdHraCdKGR1fg5KPUftcs2bhlGCQ9EJfznlmmxlmeKYQ0wPzNSRJqb5KeqalWAiz50v+VlDFUeVTX2v40LygNvhmyRHA8kExbFqAY10JL3lZxt8xxlCDbFG8Le/jfmQ6Dfwtbh6dr/irJ9WHrVPsLINblpj4e03RPhrj3P2w= Content-Type: multipart/mixed; boundary="_002_DBBPR08MB477531D6D8F34EF4BE4A885A9B710DBBPR08MB4775eurp_" MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; Return-Path: Srinath.Parvathaneni@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT036.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 24721f53-dda2-4320-c9f3-08d76936be6f X-IsSubscribed: yes X-SW-Source: 2019-11/txt/msg01277.txt.bz2 --_002_DBBPR08MB477531D6D8F34EF4BE4A885A9B710DBBPR08MB4775eurp_ Content-Type: text/plain; charset="us-ascii" Content-ID: <81314DF21349C34A837AE78D8F183F99@eurprd08.prod.outlook.com> Content-Transfer-Encoding: quoted-printable Content-length: 74009 Hello, This patch supports following MVE ACLE intrinsics which are aliases of vstr= and vldr intrinsics. vst1q_p_u8, vst1q_p_s8, vld1q_z_u8, vld1q_z_s8, vst1q_p_u16, vst1q_p_s16, vld1q_z_u16, vld1q_z_s16, vst1q_p_u32, vst1q_p_s32, vld1q_z_u32, vld1q_z_s3= 2, vld1q_z_f16, vst1q_p_f16, vld1q_z_f32, vst1q_p_f32. This patch also supports following MVE ACLE vector deinterleaving loads and= vector interleaving stores. vst2q_s8, vst2q_u8, vld2q_s8, vld2q_u8, vld4q_s8, vld4q_u8, vst2q_s16, vst2= q_u16, vld2q_s16, vld2q_u16, vld4q_s16, vld4q_u16, vst2q_s32, vst2q_u32, vld2q_s32, vld2q_u32, vld4q_s32, vld4q_u32, vld4q_f16, vld2q_f16, vst2q_f16, vld4q_f32, vld2q_f32, vst2q_f32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more d= etails. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/heli= um/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-08 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vst1q_p_u8): Define macro. (vst1q_p_s8): Likewise. (vst2q_s8): Likewise. (vst2q_u8): Likewise. (vld1q_z_u8): Likewise. (vld1q_z_s8): Likewise. (vld2q_s8): Likewise. (vld2q_u8): Likewise. (vld4q_s8): Likewise. (vld4q_u8): Likewise. (vst1q_p_u16): Likewise. (vst1q_p_s16): Likewise. (vst2q_s16): Likewise. (vst2q_u16): Likewise. (vld1q_z_u16): Likewise. (vld1q_z_s16): Likewise. (vld2q_s16): Likewise. (vld2q_u16): Likewise. (vld4q_s16): Likewise. (vld4q_u16): Likewise. (vst1q_p_u32): Likewise. (vst1q_p_s32): Likewise. (vst2q_s32): Likewise. (vst2q_u32): Likewise. (vld1q_z_u32): Likewise. (vld1q_z_s32): Likewise. (vld2q_s32): Likewise. (vld2q_u32): Likewise. (vld4q_s32): Likewise. (vld4q_u32): Likewise. (vld4q_f16): Likewise. (vld2q_f16): Likewise. (vld1q_z_f16): Likewise. (vst2q_f16): Likewise. (vst1q_p_f16): Likewise. (vld4q_f32): Likewise. (vld2q_f32): Likewise. (vld1q_z_f32): Likewise. (vst2q_f32): Likewise. (vst1q_p_f32): Likewise. (__arm_vst1q_p_u8): Define intrinsic. (__arm_vst1q_p_s8): Likewise. (__arm_vst2q_s8): Likewise. (__arm_vst2q_u8): Likewise. (__arm_vld1q_z_u8): Likewise. (__arm_vld1q_z_s8): Likewise. (__arm_vld2q_s8): Likewise. (__arm_vld2q_u8): Likewise. (__arm_vld4q_s8): Likewise. (__arm_vld4q_u8): Likewise. (__arm_vst1q_p_u16): Likewise. (__arm_vst1q_p_s16): Likewise. (__arm_vst2q_s16): Likewise. (__arm_vst2q_u16): Likewise. (__arm_vld1q_z_u16): Likewise. (__arm_vld1q_z_s16): Likewise. (__arm_vld2q_s16): Likewise. (__arm_vld2q_u16): Likewise. (__arm_vld4q_s16): Likewise. (__arm_vld4q_u16): Likewise. (__arm_vst1q_p_u32): Likewise. (__arm_vst1q_p_s32): Likewise. (__arm_vst2q_s32): Likewise. (__arm_vst2q_u32): Likewise. (__arm_vld1q_z_u32): Likewise. (__arm_vld1q_z_s32): Likewise. (__arm_vld2q_s32): Likewise. (__arm_vld2q_u32): Likewise. (__arm_vld4q_s32): Likewise. (__arm_vld4q_u32): Likewise. (__arm_vld4q_f16): Likewise. (__arm_vld2q_f16): Likewise. (__arm_vld1q_z_f16): Likewise. (__arm_vst2q_f16): Likewise. (__arm_vst1q_p_f16): Likewise. (__arm_vld4q_f32): Likewise. (__arm_vld2q_f32): Likewise. (__arm_vld1q_z_f32): Likewise. (__arm_vst2q_f32): Likewise. (__arm_vst1q_p_f32): Likewise. (vld1q_z): Define polymorphic variant. (vld2q): Likewise. (vld4q): Likewise. (vst1q_p): Likewise. (vst2q): Likewise. * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier. (LOAD1): Likewise. * config/arm/mve.md (mve_vst2q): Define RTL pattern. (mve_vld2q): Likewise. (mve_vld4q): Likewise. gcc/testsuite/ChangeLog: 2019-11-08 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: New test. * gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld2q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise. ############### Attachment also inlined for ease of reply ##########= ##### diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 1704b622c5d6e0abcf814ae1d439bb732f0bd76e..d0259d7bd96c565d901b7634e9f= 735e0e14bc9dc 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -2466,6 +2466,46 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vsbcq_u32(__a, __b, __carry) __arm_vsbcq_u32(__a, __b, __carry) #define vsbcq_m_s32(__inactive, __a, __b, __carry, __p) __arm_vsbcq_m_s32= (__inactive, __a, __b, __carry, __p) #define vsbcq_m_u32(__inactive, __a, __b, __carry, __p) __arm_vsbcq_m_u32= (__inactive, __a, __b, __carry, __p) +#define vst1q_p_u8(__addr, __value, __p) __arm_vst1q_p_u8(__addr, __value,= __p) +#define vst1q_p_s8(__addr, __value, __p) __arm_vst1q_p_s8(__addr, __value,= __p) +#define vst2q_s8(__addr, __value) __arm_vst2q_s8(__addr, __value) +#define vst2q_u8(__addr, __value) __arm_vst2q_u8(__addr, __value) +#define vld1q_z_u8(__base, __p) __arm_vld1q_z_u8(__base, __p) +#define vld1q_z_s8(__base, __p) __arm_vld1q_z_s8(__base, __p) +#define vld2q_s8(__addr) __arm_vld2q_s8(__addr) +#define vld2q_u8(__addr) __arm_vld2q_u8(__addr) +#define vld4q_s8(__addr) __arm_vld4q_s8(__addr) +#define vld4q_u8(__addr) __arm_vld4q_u8(__addr) +#define vst1q_p_u16(__addr, __value, __p) __arm_vst1q_p_u16(__addr, __valu= e, __p) +#define vst1q_p_s16(__addr, __value, __p) __arm_vst1q_p_s16(__addr, __valu= e, __p) +#define vst2q_s16(__addr, __value) __arm_vst2q_s16(__addr, __value) +#define vst2q_u16(__addr, __value) __arm_vst2q_u16(__addr, __value) +#define vld1q_z_u16(__base, __p) __arm_vld1q_z_u16(__base, __p) +#define vld1q_z_s16(__base, __p) __arm_vld1q_z_s16(__base, __p) +#define vld2q_s16(__addr) __arm_vld2q_s16(__addr) +#define vld2q_u16(__addr) __arm_vld2q_u16(__addr) +#define vld4q_s16(__addr) __arm_vld4q_s16(__addr) +#define vld4q_u16(__addr) __arm_vld4q_u16(__addr) +#define vst1q_p_u32(__addr, __value, __p) __arm_vst1q_p_u32(__addr, __valu= e, __p) +#define vst1q_p_s32(__addr, __value, __p) __arm_vst1q_p_s32(__addr, __valu= e, __p) +#define vst2q_s32(__addr, __value) __arm_vst2q_s32(__addr, __value) +#define vst2q_u32(__addr, __value) __arm_vst2q_u32(__addr, __value) +#define vld1q_z_u32(__base, __p) __arm_vld1q_z_u32(__base, __p) +#define vld1q_z_s32(__base, __p) __arm_vld1q_z_s32(__base, __p) +#define vld2q_s32(__addr) __arm_vld2q_s32(__addr) +#define vld2q_u32(__addr) __arm_vld2q_u32(__addr) +#define vld4q_s32(__addr) __arm_vld4q_s32(__addr) +#define vld4q_u32(__addr) __arm_vld4q_u32(__addr) +#define vld4q_f16(__addr) __arm_vld4q_f16(__addr) +#define vld2q_f16(__addr) __arm_vld2q_f16(__addr) +#define vld1q_z_f16(__base, __p) __arm_vld1q_z_f16(__base, __p) +#define vst2q_f16(__addr, __value) __arm_vst2q_f16(__addr, __value) +#define vst1q_p_f16(__addr, __value, __p) __arm_vst1q_p_f16(__addr, __valu= e, __p) +#define vld4q_f32(__addr) __arm_vld4q_f32(__addr) +#define vld2q_f32(__addr) __arm_vld2q_f32(__addr) +#define vld1q_z_f32(__base, __p) __arm_vld1q_z_f32(__base, __p) +#define vst2q_f32(__addr, __value) __arm_vst2q_f32(__addr, __value) +#define vst1q_p_f32(__addr, __value, __p) __arm_vst1q_p_f32(__addr, __valu= e, __p) #endif =20 __extension__ extern __inline void @@ -16085,6 +16125,252 @@ __arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x= 4_t __a, uint32x4_t __b, unsign return __res; } =20 +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_u8 (uint8_t * __addr, uint8x16_t __value, mve_pred16_t __p) +{ + return vstrbq_p_u8 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_s8 (int8_t * __addr, int8x16_t __value, mve_pred16_t __p) +{ + return vstrbq_p_s8 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_s8 (int8_t * __addr, int8x16x2_t __value) +{ + union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst2qv16qi ((__builtin_neon_qi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_u8 (uint8_t * __addr, uint8x16x2_t __value) +{ + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst2qv16qi ((__builtin_neon_qi *) __addr, __rv.__o); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_u8 (uint8_t const *__base, mve_pred16_t __p) +{ + return vldrbq_z_u8 ( __base, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_s8 (int8_t const *__base, mve_pred16_t __p) +{ + return vldrbq_z_s8 ( __base, __p); +} + +__extension__ extern __inline int8x16x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_s8 (int8_t const * __addr) +{ + union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o =3D __builtin_mve_vld2qv16qi ((__builtin_neon_qi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint8x16x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_u8 (uint8_t const * __addr) +{ + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o =3D __builtin_mve_vld2qv16qi ((__builtin_neon_qi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline int8x16x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_s8 (int8_t const * __addr) +{ + union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o =3D __builtin_mve_vld4qv16qi ((__builtin_neon_qi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint8x16x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_u8 (uint8_t const * __addr) +{ + union { uint8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o =3D __builtin_mve_vld4qv16qi ((__builtin_neon_qi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_u16 (uint16_t * __addr, uint16x8_t __value, mve_pred16_t __p) +{ + return vstrhq_p_u16 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_s16 (int16_t * __addr, int16x8_t __value, mve_pred16_t __p) +{ + return vstrhq_p_s16 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_s16 (int16_t * __addr, int16x8x2_t __value) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst2qv8hi ((__builtin_neon_hi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_u16 (uint16_t * __addr, uint16x8x2_t __value) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst2qv8hi ((__builtin_neon_hi *) __addr, __rv.__o); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_u16 (uint16_t const *__base, mve_pred16_t __p) +{ + return vldrhq_z_u16 ( __base, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_s16 (int16_t const *__base, mve_pred16_t __p) +{ + return vldrhq_z_s16 ( __base, __p); +} + +__extension__ extern __inline int16x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_s16 (int16_t const * __addr) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o =3D __builtin_mve_vld2qv8hi ((__builtin_neon_hi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint16x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_u16 (uint16_t const * __addr) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o =3D __builtin_mve_vld2qv8hi ((__builtin_neon_hi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline int16x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_s16 (int16_t const * __addr) +{ + union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o =3D __builtin_mve_vld4qv8hi ((__builtin_neon_hi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint16x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_u16 (uint16_t const * __addr) +{ + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o =3D __builtin_mve_vld4qv8hi ((__builtin_neon_hi *) __addr); + return __rv.__i; +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_u32 (uint32_t * __addr, uint32x4_t __value, mve_pred16_t __p) +{ + return vstrwq_p_u32 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_s32 (int32_t * __addr, int32x4_t __value, mve_pred16_t __p) +{ + return vstrwq_p_s32 (__addr, __value, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_s32 (int32_t * __addr, int32x4x2_t __value) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst2qv4si ((__builtin_neon_si *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_u32 (uint32_t * __addr, uint32x4x2_t __value) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst2qv4si ((__builtin_neon_si *) __addr, __rv.__o); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_u32 (uint32_t const *__base, mve_pred16_t __p) +{ + return vldrwq_z_u32 ( __base, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_s32 (int32_t const *__base, mve_pred16_t __p) +{ + return vldrwq_z_s32 ( __base, __p); +} + +__extension__ extern __inline int32x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_s32 (int32_t const * __addr) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o =3D __builtin_mve_vld2qv4si ((__builtin_neon_si *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint32x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_u32 (uint32_t const * __addr) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o =3D __builtin_mve_vld2qv4si ((__builtin_neon_si *) __addr); + return __rv.__i; +} + +__extension__ extern __inline int32x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_s32 (int32_t const * __addr) +{ + union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o =3D __builtin_mve_vld4qv4si ((__builtin_neon_si *) __addr); + return __rv.__i; +} + +__extension__ extern __inline uint32x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_u32 (uint32_t const * __addr) +{ + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o =3D __builtin_mve_vld4qv4si ((__builtin_neon_si *) __addr); + return __rv.__i; +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ =20 __extension__ extern __inline void @@ -19436,6 +19722,88 @@ __arm_vrev64q_x_f32 (float32x4_t __a, mve_pred16_t= __p) return __builtin_mve_vrev64q_m_fv4sf (vuninitializedq_f32 (), __a, __p); } =20 +__extension__ extern __inline float16x8x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_f16 (float16_t const * __addr) +{ + union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o =3D __builtin_mve_vld4qv8hf (__addr); + return __rv.__i; +} + +__extension__ extern __inline float16x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_f16 (float16_t const * __addr) +{ + union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o =3D __builtin_mve_vld2qv8hf (__addr); + return __rv.__i; +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_f16 (float16_t const *__base, mve_pred16_t __p) +{ + return vldrhq_z_f16 ( __base, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_f16 (float16_t * __addr, float16x8x2_t __value) +{ + union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst2qv8hf (__addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t _= _p) +{ + return vstrhq_p_f16 (__addr, __value, __p); +} + +__extension__ extern __inline float32x4x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld4q_f32 (float32_t const * __addr) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__o =3D __builtin_mve_vld4qv4sf (__addr); + return __rv.__i; +} + +__extension__ extern __inline float32x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld2q_f32 (float32_t const * __addr) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o =3D __builtin_mve_vld2qv4sf (__addr); + return __rv.__i; +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_z_f32 (float32_t const *__base, mve_pred16_t __p) +{ + return vldrwq_z_f32 ( __base, __p); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst2q_f32 (float32_t * __addr, float32x4x2_t __value) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst2qv4sf (__addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst1q_p_f32 (float32_t * __addr, float32x4_t __value, mve_pred16_t _= _p) +{ + return vstrwq_p_f32 (__addr, __value, __p); +} + #endif =20 enum { @@ -20995,6 +21363,42 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld1q_f16 (__ARM_mve_= coerce(__p0, float16_t const *)), \ int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld1q_f32 (__ARM_mve_= coerce(__p0, float32_t const *)));}) =20 +#define vld1q_z(p0,p1) __arm_vld1q_z(p0, p1) +#define __arm_vld1q_z(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_z_s8 (__ARM_mve_co= erce(__p0, int8_t const *), p1), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_z_s16 (__ARM_mve_= coerce(__p0, int16_t const *), p1), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_z_s32 (__ARM_mve_= coerce(__p0, int32_t const *), p1), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_z_u8 (__ARM_mve_c= oerce(__p0, uint8_t const *), p1), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_z_u16 (__ARM_mve= _coerce(__p0, uint16_t const *), p1), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_z_u32 (__ARM_mve= _coerce(__p0, uint32_t const *), p1), \ + int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld1q_z_f16 (__ARM_mv= e_coerce(__p0, float16_t const *), p1), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld1q_z_f32 (__ARM_mv= e_coerce(__p0, float32_t const *), p1));}) + +#define vld2q(p0) __arm_vld2q(p0) +#define __arm_vld2q(p0) ({ __typeof(p0) __p0 =3D (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld2q_s8 (__ARM_mve_coer= ce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld2q_s16 (__ARM_mve_co= erce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld2q_s32 (__ARM_mve_co= erce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld2q_u8 (__ARM_mve_coe= rce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld2q_u16 (__ARM_mve_c= oerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld2q_u32 (__ARM_mve_c= oerce(__p0, uint32_t const *)), \ + int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld2q_f16 (__ARM_mve_= coerce(__p0, float16_t const *)), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld2q_f32 (__ARM_mve_= coerce(__p0, float32_t const *)));}) + +#define vld4q(p0) __arm_vld4q(p0) +#define __arm_vld4q(p0) ({ __typeof(p0) __p0 =3D (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld4q_s8 (__ARM_mve_coer= ce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld4q_s16 (__ARM_mve_co= erce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld4q_s32 (__ARM_mve_co= erce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld4q_u8 (__ARM_mve_coe= rce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld4q_u16 (__ARM_mve_c= oerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld4q_u32 (__ARM_mve_c= oerce(__p0, uint32_t const *)), \ + int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld4q_f16 (__ARM_mve_= coerce(__p0, float16_t const *)), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld4q_f32 (__ARM_mve_= coerce(__p0, float32_t const *)));}) + #define vldrhq_gather_offset(p0,p1) __arm_vldrhq_gather_offset(p0,p1) #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ __typeof(p1) __p1 =3D (p1); \ @@ -21063,6 +21467,32 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vldrwq_gather_shifted_= offset_z_u32 (__ARM_mve_coerce(__p0, uint32_t const *), p1, p2), \ int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vldrwq_gather_shifted= _offset_z_f32 (__ARM_mve_coerce(__p0, float32_t const *), p1, p2));}) =20 +#define vst1q_p(p0,p1,p2) __arm_vst1q_p(p0,p1,p2) +#define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1= q_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)= , p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst= 1q_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8= _t), p2), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst= 1q_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4= _t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vs= t1q_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x1= 6_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_v= st1q_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint= 16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_v= st1q_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint= 32x4_t), p2), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm= _vst1q_p_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, f= loat16x8_t), p2), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm= _vst1q_p_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, f= loat32x4_t), p2));}) + +#define vst2q(p0,p1) __arm_vst2q(p0,p1) +#define __arm_vst2q(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vs= t2q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_= t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_v= st2q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8= x2_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_v= st2q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4= x2_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_= vst2q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x1= 6x2_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm= _vst2q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint= 16x8x2_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm= _vst2q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint= 32x4x2_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __a= rm_vst2q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, f= loat16x8x2_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __a= rm_vst2q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, f= loat32x4x2_t)));}) + #define vst1q(p0,p1) __arm_vst1q(p0,p1) #define __arm_vst1q(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ __typeof(p1) __p1 =3D (p1); \ @@ -24774,6 +25204,28 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_v= st1q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16= x8_t)), \ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_v= st1q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32= x4_t)));}) =20 +#define vst1q_p(p0,p1,p2) __arm_vst1q_p(p0,p1,p2) +#define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1= q_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)= , p2), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst= 1q_p_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8= _t), p2), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst= 1q_p_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4= _t), p2), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vs= t1q_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x1= 6_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_v= st1q_p_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint= 16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_v= st1q_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint= 32x4_t), p2));}) + +#define vst2q(p0,p1) __arm_vst2q(p0,p1) +#define __arm_vst2q(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vs= t2q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_= t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_v= st2q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8= x2_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_v= st2q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4= x2_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_= vst2q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x1= 6x2_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm= _vst2q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint= 16x8x2_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm= _vst2q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint= 32x4x2_t)));}) + #define vstrhq(p0,p1) __arm_vstrhq(p0,p1) #define __arm_vstrhq(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ __typeof(p1) __p1 =3D (p1); \ @@ -25780,6 +26232,36 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsbcq= _s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),= p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsb= cq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4= _t), p2));}) =20 +#define vld1q_z(p0,p1) __arm_vld1q_z(p0, p1) +#define __arm_vld1q_z(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_z_s8 (__ARM_mve_co= erce(__p0, int8_t const *), p1), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_z_s16 (__ARM_mve_= coerce(__p0, int16_t const *), p1), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_z_s32 (__ARM_mve_= coerce(__p0, int32_t const *), p1), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_z_u8 (__ARM_mve_c= oerce(__p0, uint8_t const *), p1), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_z_u16 (__ARM_mve= _coerce(__p0, uint16_t const *), p1), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_z_u32 (__ARM_mve= _coerce(__p0, uint32_t const *), p1));}) + +#define vld2q(p0) __arm_vld2q(p0) +#define __arm_vld2q(p0) ({ __typeof(p0) __p0 =3D (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld2q_s8 (__ARM_mve_coer= ce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld2q_s16 (__ARM_mve_co= erce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld2q_s32 (__ARM_mve_co= erce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld2q_u8 (__ARM_mve_coe= rce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld2q_u16 (__ARM_mve_c= oerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld2q_u32 (__ARM_mve_c= oerce(__p0, uint32_t const *)));}) + +#define vld4q(p0) __arm_vld4q(p0) +#define __arm_vld4q(p0) ({ __typeof(p0) __p0 =3D (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld4q_s8 (__ARM_mve_coer= ce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld4q_s16 (__ARM_mve_co= erce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld4q_s32 (__ARM_mve_co= erce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld4q_u8 (__ARM_mve_coe= rce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld4q_u16 (__ARM_mve_c= oerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld4q_u32 (__ARM_mve_c= oerce(__p0, uint32_t const *)));}) + #endif /* MVE Floating point. */ =20 #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_b= uiltins.def index a413b38676f2f102c16fdf2147f3b8a4d8ec47b4..638dcbc819034bf2c8428ff40f0= e4d811763d80e 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -873,3 +873,6 @@ VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbciq_m_s, v4s= i) VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbciq_m_u, v4si) VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbcq_m_s, v4si) VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbcq_m_u, v4si) +VAR5 (STORE1, vst2q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR5 (LOAD1, vld4q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR5 (LOAD1, vld2q, v16qi, v8hi, v4si, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 8ff69094378396830ef31d9e2ca9db71c58aefab..62735e5ddab1125e6f38fbf5a5c= b5c04936a7717 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -214,7 +214,7 @@ VLDRDQGBWB_S VLDRDQGBWB_U VADCQ_U VADCQ_M_U VADCQ_S VADCQ_M_S VSBCIQ_U VSBCIQ_S VSBCIQ_M_U VSBCIQ_M_S VSBCQ_U VSBCQ_S VSBCQ_M_U VSBCQ_M_S VADCIQ_U VADCIQ_M_U - VADCIQ_S VADCIQ_M_S]) + VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q]) =20 (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -10775,3 +10775,91 @@ "vsbc.i32\t%q0, %q1, %q2" [(set_attr "type" "mve_move") (set_attr "length" "4")]) + +;; +;; [vst2q]) +;; +(define_insn "mve_vst2q" + [(set (match_operand:OI 0 "neon_struct_operand" "=3DUm") + (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") + (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + VST2Q)) + ] + "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))" +{ + rtx ops[4]; + int regno =3D REGNO (operands[1]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D gen_rtx_REG (TImode, regno + 4); + rtx reg =3D operands[0]; + while (reg && !REG_P (reg)) + reg =3D XEXP (reg, 0); + gcc_assert (REG_P (reg)); + ops[2] =3D reg; + ops[3] =3D operands[0]; + output_asm_insn ("vst20.\t{%q0, %q1}, [%2]\n\t" + "vst21.\t{%q0, %q1}, %3", ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vld2q]) +;; +(define_insn "mve_vld2q" + [(set (match_operand:OI 0 "s_register_operand" "=3Dw") + (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") + (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + VLD2Q)) + ] + "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))" +{ + rtx ops[4]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D gen_rtx_REG (TImode, regno + 4); + rtx reg =3D operands[1]; + while (reg && !REG_P (reg)) + reg =3D XEXP (reg, 0); + gcc_assert (REG_P (reg)); + ops[2] =3D reg; + ops[3] =3D operands[1]; + output_asm_insn ("vld20.\t{%q0, %q1}, [%2]\n\t" + "vld21.\t{%q0, %q1}, %3", ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vld4q]) +;; +(define_insn "mve_vld4q" + [(set (match_operand:XI 0 "s_register_operand" "=3Dw") + (unspec:XI [(match_operand:XI 1 "neon_struct_operand" "Um") + (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + VLD4Q)) + ] + "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))" +{ + rtx ops[6]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D gen_rtx_REG (TImode, regno+4); + ops[2] =3D gen_rtx_REG (TImode, regno+8); + ops[3] =3D gen_rtx_REG (TImode, regno + 12); + rtx reg =3D operands[1]; + while (reg && !REG_P (reg)) + reg =3D XEXP (reg, 0); + gcc_assert (REG_P (reg)); + ops[4] =3D reg; + ops[5] =3D operands[1]; + output_asm_insn ("vld40.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vld41.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vld42.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vld43.\t{%q0, %q1, %q2, %q3}, %5", ops); + return ""; +} + [(set_attr "length" "16")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..26cc62ad29870209d51fb6133e3= 5a55bbc254d57 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base, mve_pred16_t p) +{ + return vld1q_z_f16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.f16" } } */ + +float16x8_t +foo1 (float16_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrht.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..9184987dd5ae2d5b0de75e08e49= d5149559a7aef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base, mve_pred16_t p) +{ + return vld1q_z_f32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.f32" } } */ + +float32x4_t +foo1 (float32_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..c993f00fea3cfcc19531e20d161= b120570794997 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, mve_pred16_t p) +{ + return vld1q_z_s16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.s16" } } */ + +int16x8_t +foo1 (int16_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..801d6c08f16339075ecccaca505= c5b55360b5c84 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base, mve_pred16_t p) +{ + return vld1q_z_s32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.s32" } } */ + +int32x4_t +foo1 (int32_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..edbffd1804da364ce2bf44cb587= 441a7e774a898 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base, mve_pred16_t p) +{ + return vld1q_z_s8 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.s8" } } */ + +int8x16_t +foo1 (int8_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..c9c0edb2e4dfc098b67b9148980= 897b42d199388 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, mve_pred16_t p) +{ + return vld1q_z_u16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..34b84cddef49798dabd167eddad= 1c784708aab55 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base, mve_pred16_t p) +{ + return vld1q_z_u32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ + +uint32x4_t +foo1 (uint32_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..9338a98d3c0eba57a65f908c70d= 8801c57b87a12 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base, mve_pred16_t p) +{ + return vld1q_z_u8 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ + +uint8x16_t +foo1 (uint8_t const * base, mve_pred16_t p) +{ + return vld1q_z (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..9ac3ae203e9fdfa77ed281a74a9= 89a34fd1c8949 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float16x8x2_t +foo (float16_t const * addr) +{ + return vld2q_f16 (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ +/* { dg-final { scan-assembler "vld21.16" } } */ + +float16x8x2_t +foo1 (float16_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..f2ef313af6cec813db59a772cee= e87dab090be3e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float32x4x2_t +foo (float32_t const * addr) +{ + return vld2q_f32 (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ +/* { dg-final { scan-assembler "vld21.32" } } */ + +float32x4x2_t +foo1 (float32_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..9d1a8bfebb0501063833666c7f3= ea5a3f1e40de0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8x2_t +foo (int16_t const * addr) +{ + return vld2q_s16 (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ +/* { dg-final { scan-assembler "vld21.16" } } */ + +int16x8x2_t +foo1 (int16_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..2fcc3bbb214f1923bbd03540428= 54bde2ec6a984 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4x2_t +foo (int32_t const * addr) +{ + return vld2q_s32 (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ +/* { dg-final { scan-assembler "vld21.32" } } */ + +int32x4x2_t +foo1 (int32_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c b/gcc/t= estsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..e4ba850fbd10507e55e2a8b4f2d= 576c6ee23a465 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16x2_t +foo (int8_t const * addr) +{ + return vld2q_s8 (addr); +} + +/* { dg-final { scan-assembler "vld20.8" } } */ +/* { dg-final { scan-assembler "vld21.8" } } */ + +int8x16x2_t +foo1 (int8_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..e16bd47b4347fec79bb8dc16331= a8927075d843b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8x2_t +foo (uint16_t const * addr) +{ + return vld2q_u16 (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ +/* { dg-final { scan-assembler "vld21.16" } } */ + +uint16x8x2_t +foo1 (uint16_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..9ddad5f7dcff826342a4a07e7c4= f0bd5a278ebf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4x2_t +foo (uint32_t const * addr) +{ + return vld2q_u32 (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ +/* { dg-final { scan-assembler "vld21.32" } } */ + +uint32x4x2_t +foo1 (uint32_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c b/gcc/t= estsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..76ae541b27ce6bd36c41f2325bb= 4ff1f932e8eb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16x2_t +foo (uint8_t const * addr) +{ + return vld2q_u8 (addr); +} + +/* { dg-final { scan-assembler "vld20.8" } } */ +/* { dg-final { scan-assembler "vld21.8" } } */ + +uint8x16x2_t +foo1 (uint8_t const * addr) +{ + return vld2q (addr); +} + +/* { dg-final { scan-assembler "vld20.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..6dcfe7ea454e975744854340c5f= 13ef0cc238afb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float16x8x4_t +foo (float16_t const * addr) +{ + return vld4q_f16 (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ +/* { dg-final { scan-assembler "vld41.16" } } */ +/* { dg-final { scan-assembler "vld42.16" } } */ +/* { dg-final { scan-assembler "vld43.16" } } */ + +float16x8x4_t +foo1 (float16_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..a7c1b1608d69148285dbc1e801e= f8f69b64019d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float32x4x4_t +foo (float32_t const * addr) +{ + return vld4q_f32 (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ +/* { dg-final { scan-assembler "vld41.32" } } */ +/* { dg-final { scan-assembler "vld42.32" } } */ +/* { dg-final { scan-assembler "vld43.32" } } */ + +float32x4x4_t +foo1 (float32_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..6f79d92911ec771a6493510fd08= c93d30103d9b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8x4_t +foo (int16_t const * addr) +{ + return vld4q_s16 (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ +/* { dg-final { scan-assembler "vld41.16" } } */ +/* { dg-final { scan-assembler "vld42.16" } } */ +/* { dg-final { scan-assembler "vld43.16" } } */ + +int16x8x4_t +foo1 (int16_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..d7bc46ea9512aa197327584aef3= 235c0ee51ca52 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4x4_t +foo (int32_t const * addr) +{ + return vld4q_s32 (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ +/* { dg-final { scan-assembler "vld41.32" } } */ +/* { dg-final { scan-assembler "vld42.32" } } */ +/* { dg-final { scan-assembler "vld43.32" } } */ + +int32x4x4_t +foo1 (int32_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c b/gcc/t= estsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..3708b59f6ec77cd3ecda9e06f21= 3d1f02a482151 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16x4_t +foo (int8_t const * addr) +{ + return vld4q_s8 (addr); +} + +/* { dg-final { scan-assembler "vld40.8" } } */ +/* { dg-final { scan-assembler "vld41.8" } } */ +/* { dg-final { scan-assembler "vld42.8" } } */ +/* { dg-final { scan-assembler "vld43.8" } } */ + +int8x16x4_t +foo1 (int8_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..2b708bd1cbd167d8a909bc9c554= e1b9269a81240 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8x4_t +foo (uint16_t const * addr) +{ + return vld4q_u16 (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ +/* { dg-final { scan-assembler "vld41.16" } } */ +/* { dg-final { scan-assembler "vld42.16" } } */ +/* { dg-final { scan-assembler "vld43.16" } } */ + +uint16x8x4_t +foo1 (uint16_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..9b3c3922f1bb76b52de86a59dd4= 777431e793cb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4x4_t +foo (uint32_t const * addr) +{ + return vld4q_u32 (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ +/* { dg-final { scan-assembler "vld41.32" } } */ +/* { dg-final { scan-assembler "vld42.32" } } */ +/* { dg-final { scan-assembler "vld43.32" } } */ + +uint32x4x4_t +foo1 (uint32_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c b/gcc/t= estsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..e950326e0ef4a388cbe1d58098b= 49d8862c0419e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16x4_t +foo (uint8_t const * addr) +{ + return vld4q_u8 (addr); +} + +/* { dg-final { scan-assembler "vld40.8" } } */ +/* { dg-final { scan-assembler "vld41.8" } } */ +/* { dg-final { scan-assembler "vld42.8" } } */ +/* { dg-final { scan-assembler "vld43.8" } } */ + +uint8x16x4_t +foo1 (uint8_t const * addr) +{ + return vld4q (addr); +} + +/* { dg-final { scan-assembler "vld40.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..9983da6ba3f67e26be7db6ccbed= 7a684dbc2943e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (float16_t * addr, float16x8_t value, mve_pred16_t p) +{ + vst1q_p_f16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..870d2e257ab26a2978e00a4c5f7= 7b7154592e671 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (float32_t * addr, float32x4_t value, mve_pred16_t p) +{ + vst1q_p_f32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..71dc898480f15ed6586eeff4bbb= 67307a5e77794 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int16x8_t value, mve_pred16_t p) +{ + vst1q_p_s16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..8643c5068d629dfce628f6d08b5= 81bdd56f117ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (int32_t * addr, int32x4_t value, mve_pred16_t p) +{ + vst1q_p_s32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..570574fc2b995fab882d424a4bc= b6d997d155f58 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16_t value, mve_pred16_t p) +{ + vst1q_p_s8 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ + +void +foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..43fc3ae023d942598df1c43066c= 79285d5a59c66 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p) +{ + vst1q_p_u16 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ + +void +foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrht.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..bcaf6f23597c45977661eede690= 786890c051e5d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p) +{ + vst1q_p_u32 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ + +void +foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrwt.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..898d2eb10835a50a689d4db6dfe= 50425b6c40769 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p) +{ + vst1q_p_u8 (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p) +{ + vst1q_p (addr, value, p); +} + +/* { dg-final { scan-assembler "vstrbt.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..8c3e621320e6aa3900fafeaeab3= db9f9fd1dae06 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (float16_t * addr, float16x8x2_t value) +{ + vst2q_f16 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ +/* { dg-final { scan-assembler "vst21.16" } } */ + +void +foo1 (float16_t * addr, float16x8x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..99648c3db93a241088efb08df52= 99d651002d288 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (float32_t * addr, float32x4x2_t value) +{ + vst2q_f32 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ +/* { dg-final { scan-assembler "vst21.32" } } */ + +void +foo1 (float32_t * addr, float32x4x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..8b44d7eab4eefcf242ef794a678= 1a67836638099 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int16x8x2_t value) +{ + vst2q_s16 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ +/* { dg-final { scan-assembler "vst21.16" } } */ + +void +foo1 (int16_t * addr, int16x8x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..7102edbb0e19081d43bf5810429= cab9c79fa330d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (int32_t * addr, int32x4x2_t value) +{ + vst2q_s32 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ +/* { dg-final { scan-assembler "vst21.32" } } */ + +void +foo1 (int32_t * addr, int32x4x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c b/gcc/t= estsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..c16a1042f323eaa877930479312= 58d683517f6a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16x2_t value) +{ + vst2q_s8 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.8" } } */ +/* { dg-final { scan-assembler "vst21.8" } } */ + +void +foo1 (int8_t * addr, int8x16x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..69c97be5df9a876ee7715025587= 8f5765f31a963 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint16x8x2_t value) +{ + vst2q_u16 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ +/* { dg-final { scan-assembler "vst21.16" } } */ + +void +foo1 (uint16_t * addr, uint16x8x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..aba5a20abc0b239cca5352aa81f= 17d8a56069164 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (uint32_t * addr, uint32x4x2_t value) +{ + vst2q_u32 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ +/* { dg-final { scan-assembler "vst21.32" } } */ + +void +foo1 (uint32_t * addr, uint32x4x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c b/gcc/t= estsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..4dc1f82380473243f2e1b1adee4= af97289f59261 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16x2_t value) +{ + vst2q_u8 (addr, value); +} + +/* { dg-final { scan-assembler "vst20.8" } } */ +/* { dg-final { scan-assembler "vst21.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16x2_t value) +{ + vst2q (addr, value); +} + +/* { dg-final { scan-assembler "vst20.8" } } */ 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