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Thu, 14 Nov 2019 19:13:21 +0000 From: Srinath Parvathaneni To: "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov Subject: [PATCH][ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. Date: Thu, 14 Nov 2019 19:15:00 -0000 Message-ID: References: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> In-Reply-To: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-PUrlCount: 1 x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:304;OLM:304; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(1496009)(4636009)(39860400002)(396003)(366004)(376002)(346002)(136003)(54534003)(199004)(189003)(81156014)(316002)(81166006)(30864003)(2501003)(44832011)(4326008)(74316002)(7696005)(99286004)(478600001)(186003)(11346002)(26005)(54906003)(76176011)(52536014)(5660300002)(446003)(25786009)(71190400001)(71200400001)(33656002)(66946007)(52116002)(305945005)(66556008)(7736002)(66446008)(66476007)(66616009)(64756008)(256004)(5024004)(9686003)(966005)(5640700003)(3846002)(66066001)(6916009)(86362001)(486006)(6506007)(6436002)(14454004)(8936002)(2906002)(6116002)(2351001)(55016002)(8676002)(102836004)(386003)(476003)(6306002)(579004)(559001);DIR:OUT;SFP:1101;SCL:1;SRVR:DBBPR08MB4807;H:DBBPR08MB4775.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: EJyvT5GgP+FSRH2nW6Uyg0rHGmgPkASHjk1EoMn7St68GsQRuqNt7xloMrmIUI91q91bXmyyWA3HozUpyZdD9yixRTRe1FFS+C4sdi84+AcIKJkxa4YKFa9Dudtfop25yxEvWXykm4aupQSZ+KpR7DjXvkgjbhTGhlnXsGaByh03Zo7lwkk0pR82WvP36kvEjYRpGuekqzJtAO46PUmgCrNv4bfSsNPTNa0dc44+klze0IkBRAMC7dWapFJc3WwCe7N3xBwNu211Do4uVZFDi1UdFY1RIvTD1xAZ6iZCVAqmmQDc4uofbj2q23nB29errWHErt/bDt5/SX+aIdfDTPVFV34qUjOj3kf6rbrDBXfFZBkWCZznl7yOVgqmAjeDXlxmB6r8/K6fp8FJOs8SLnSSMG+O3CYWR3gZV6zOKfa/Mqlxny0MC5FroICMOl6N8ZaSG4ZKXj3xhS4ovp8sjlq2NI4WzPoDYI5A3DyA2QI= Content-Type: multipart/mixed; boundary="_002_DBBPR08MB477535B6B4E27D3FF77437CF9B710DBBPR08MB4775eurp_" MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; Return-Path: Srinath.Parvathaneni@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT004.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: b37c0457-e8af-4f6c-6e3d-08d76936b6ee X-IsSubscribed: yes X-SW-Source: 2019-11/txt/msg01263.txt.bz2 --_002_DBBPR08MB477535B6B4E27D3FF77437CF9B710DBBPR08MB4775eurp_ Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable Content-length: 29191 Hello, This patch supports the following MVE ACLE load intrinsics with zero(_z) suffix. * ``_z`` (zero) which indicates false-predicated lanes are filled with zero= es, these are only used for load instructions. vldrbq_gather_offset_z_s16, vldrbq_gather_offset_z_u8, vldrbq_gather_offset= _z_s32, vldrbq_gather_offset_z_u16, vldrbq_gather_offset_z_u32, vldrbq_gather_offse= t_z_s8, vldrbq_z_s16, vldrbq_z_u8, vldrbq_z_s8, vldrbq_z_s32, vldrbq_z_u16, vldrbq_= z_u32, vldrwq_gather_base_z_u32, vldrwq_gather_base_z_s32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more d= etails. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/hel= ium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin qualifier. (LDRGBU_Z_QUALIFIERS): Likewise. (LDRGS_Z_QUALIFIERS): Likewise. (LDRGU_Z_QUALIFIERS): Likewise. (LDRS_Z_QUALIFIERS): Likewise. (LDRU_Z_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro. (vldrbq_gather_offset_z_u8): Likewise. (vldrbq_gather_offset_z_s32): Likewise. (vldrbq_gather_offset_z_u16): Likewise. (vldrbq_gather_offset_z_u32): Likewise. (vldrbq_gather_offset_z_s8): Likewise. (vldrbq_z_s16): Likewise. (vldrbq_z_u8): Likewise. (vldrbq_z_s8): Likewise. (vldrbq_z_s32): Likewise. (vldrbq_z_u16): Likewise. (vldrbq_z_u32): Likewise. (vldrwq_gather_base_z_u32): Likewise. (vldrwq_gather_base_z_s32): Likewise. (__arm_vldrbq_gather_offset_z_s8): Define intrinsic. (__arm_vldrbq_gather_offset_z_s32): Likewise. (__arm_vldrbq_gather_offset_z_s16): Likewise. (__arm_vldrbq_gather_offset_z_u8): Likewise. (__arm_vldrbq_gather_offset_z_u32): Likewise. (__arm_vldrbq_gather_offset_z_u16): Likewise. (__arm_vldrbq_z_s8): Likewise. (__arm_vldrbq_z_s32): Likewise. (__arm_vldrbq_z_s16): Likewise. (__arm_vldrbq_z_u8): Likewise. (__arm_vldrbq_z_u32): Likewise. (__arm_vldrbq_z_u16): Likewise. (__arm_vldrwq_gather_base_z_s32): Likewise. (__arm_vldrwq_gather_base_z_u32): Likewise. (vldrbq_gather_offset_z): Define polymorphic variant. * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin qualifier. (LDRGBU_Z_QUALIFIERS): Likewise. (LDRGS_Z_QUALIFIERS): Likewise. (LDRGU_Z_QUALIFIERS): Likewise. (LDRS_Z_QUALIFIERS): Likewise. (LDRU_Z_QUALIFIERS): Likewise. * config/arm/mve.md (mve_vldrbq_gather_offset_z_): Define RTL pattern. (mve_vldrbq_z_): Likewise. (mve_vldrwq_gather_base_z_v4si): Likewise. gcc/testsuite/ChangeLog: Likewise. 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: New test. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise. ############### Attachment also inlined for ease of reply ##########= ##### diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index b5639051bf07785d906ed596e08d670f4de1a67e..c3d12375d2fbc933ad33f7a15a3= bbf53079d0639 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -653,6 +653,40 @@ arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] =3D { qualifier_unsigned, qualifier_unsigned, qualifier_immediate}; #define LDRGBU_QUALIFIERS (arm_ldrgbu_qualifiers) =20 +static enum arm_type_qualifiers +arm_ldrgbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_none, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned}; +#define LDRGBS_Z_QUALIFIERS (arm_ldrgbs_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned}; +#define LDRGBU_Z_QUALIFIERS (arm_ldrgbu_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_none, qualifier_pointer, qualifier_unsigned, + qualifier_unsigned}; +#define LDRGS_Z_QUALIFIERS (arm_ldrgs_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_unsigned, qualifier_pointer, qualifier_unsigned, + qualifier_unsigned}; +#define LDRGU_Z_QUALIFIERS (arm_ldrgu_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldrs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_none, qualifier_pointer, qualifier_unsigned}; +#define LDRS_Z_QUALIFIERS (arm_ldrs_z_qualifiers) + +static enum arm_type_qualifiers +arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_unsigned, qualifier_pointer, qualifier_unsigned}; +#define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers) + /* End of Qualifier for MVE builtins. */ =20 /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index f852acb575b596c534c474d19faa73c03cf85c5e..b40a9c238b7f883a0e91dd6fcc5= f41182ea6efe3 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1744,6 +1744,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p) __arm= _vstrbq_scatter_offset_p_u16( __base, __offset, __value, __p) #define vstrwq_scatter_base_p_s32(__addr, __offset, __value, __p) __arm_v= strwq_scatter_base_p_s32(__addr, __offset, __value, __p) #define vstrwq_scatter_base_p_u32(__addr, __offset, __value, __p) __arm_v= strwq_scatter_base_p_u32(__addr, __offset, __value, __p) +#define vldrbq_gather_offset_z_s16(__base, __offset, __p) __arm_vldrbq_gat= her_offset_z_s16(__base, __offset, __p) +#define vldrbq_gather_offset_z_u8(__base, __offset, __p) __arm_vldrbq_gath= er_offset_z_u8(__base, __offset, __p) +#define vldrbq_gather_offset_z_s32(__base, __offset, __p) __arm_vldrbq_gat= her_offset_z_s32(__base, __offset, __p) +#define vldrbq_gather_offset_z_u16(__base, __offset, __p) __arm_vldrbq_gat= her_offset_z_u16(__base, __offset, __p) +#define vldrbq_gather_offset_z_u32(__base, __offset, __p) __arm_vldrbq_gat= her_offset_z_u32(__base, __offset, __p) +#define vldrbq_gather_offset_z_s8(__base, __offset, __p) __arm_vldrbq_gath= er_offset_z_s8(__base, __offset, __p) +#define vldrbq_z_s16(__base, __p) __arm_vldrbq_z_s16(__base, __p) +#define vldrbq_z_u8(__base, __p) __arm_vldrbq_z_u8(__base, __p) +#define vldrbq_z_s8(__base, __p) __arm_vldrbq_z_s8(__base, __p) +#define vldrbq_z_s32(__base, __p) __arm_vldrbq_z_s32(__base, __p) +#define vldrbq_z_u16(__base, __p) __arm_vldrbq_z_u16(__base, __p) +#define vldrbq_z_u32(__base, __p) __arm_vldrbq_z_u32(__base, __p) +#define vldrwq_gather_base_z_u32(__addr, __offset, __p) __arm_vldrwq_gath= er_base_z_u32(__addr, __offset, __p) +#define vldrwq_gather_base_z_s32(__addr, __offset, __p) __arm_vldrwq_gath= er_base_z_s32(__addr, __offset, __p) #endif =20 __extension__ extern __inline void @@ -11330,6 +11344,105 @@ __arm_vstrwq_scatter_base_p_u32 (uint32x4_t __add= r, const int __offset, uint32x4 { __builtin_mve_vstrwq_scatter_base_p_uv4si (__addr, __offset, __value, __= p); } + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_s8 (int8_t const * __base, uint8x16_t __offse= t, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_sv16qi ((__builtin_neon_qi *= ) __base, __offset, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_s32 (int8_t const * __base, uint32x4_t __offs= et, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_sv4si ((__builtin_neon_qi *)= __base, __offset, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_s16 (int8_t const * __base, uint16x8_t __offs= et, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_sv8hi ((__builtin_neon_qi *)= __base, __offset, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_u8 (uint8_t const * __base, uint8x16_t __offs= et, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_uv16qi ((__builtin_neon_qi *= ) __base, __offset, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_u32 (uint8_t const * __base, uint32x4_t __off= set, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_uv4si ((__builtin_neon_qi *)= __base, __offset, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_z_u16 (uint8_t const * __base, uint16x8_t __off= set, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_gather_offset_z_uv8hi ((__builtin_neon_qi *)= __base, __offset, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_s8 (int8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_sv16qi ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_s32 (int8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_sv4si ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_s16 (int8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_sv8hi ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_u8 (uint8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_uv16qi ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_u32 (uint8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_uv4si ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_z_u16 (uint8_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrbq_z_uv8hi ((__builtin_neon_qi *) __base, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_z_s32 (uint32x4_t __addr, const int __offset, mve= _pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_base_z_sv4si (__addr, __offset, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_z_u32 (uint32x4_t __addr, const int __offset, mve= _pred16_t __p) +{ + return __builtin_mve_vldrwq_gather_base_z_uv4si (__addr, __offset, __p); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ =20 __extension__ extern __inline void @@ -13471,6 +13584,7 @@ __arm_vsubq_m_n_f16 (float16x8_t __inactive, float1= 6x8_t __a, float16_t __b, mve { return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p); } + #endif =20 enum { @@ -17946,6 +18060,17 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32 (p0, = p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32 (p0,= p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) =20 +#define vldrbq_gather_offset_z(p0,p1,p2) __arm_vldrbq_gather_offset_z(p0,p= 1,p2) +#define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p= 0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint8x16_t]: __a= rm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce(__p0, int8_t const *), __ARM= _mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __a= rm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce(__p0, int8_t const *), __AR= M_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __a= rm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int8_t const *), __AR= M_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint8x16_t]: __= arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce(__p0, uint8_t const *), __A= RM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __= arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint8_t const *), __= ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __= arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint8_t const *), __= ARM_mve_coerce(__p1, uint32x4_t), p2));}) + #endif /* MVE Floating point. */ =20 #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_b= uiltins.def index dc22c2f599702be5a4c4481033d3f413abf6d1c5..45b00e889cfe716a2c70fb86d72= eb9a4c411b70d 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -703,3 +703,9 @@ VAR3 (STRSS_P, vstrbq_scatter_offset_p_s, v16qi, v8hi, = v4si) VAR3 (STRSU_P, vstrbq_scatter_offset_p_u, v16qi, v8hi, v4si) VAR1 (STRSBS_P, vstrwq_scatter_base_p_s, v4si) VAR1 (STRSBU_P, vstrwq_scatter_base_p_u, v4si) +VAR1 (LDRGBS_Z, vldrwq_gather_base_z_s, v4si) +VAR1 (LDRGBU_Z, vldrwq_gather_base_z_u, v4si) +VAR3 (LDRGS_Z, vldrbq_gather_offset_z_s, v16qi, v8hi, v4si) +VAR3 (LDRGU_Z, vldrbq_gather_offset_z_u, v16qi, v8hi, v4si) +VAR3 (LDRS_Z, vldrbq_z_s, v16qi, v8hi, v4si) +VAR3 (LDRU_Z, vldrbq_z_u, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 266a7f830285521fd225c8b07bc15e412b7bab61..05b94e4ee283da427aee18c7223= bf5ff4b0e1e4a 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -8135,3 +8135,69 @@ return ""; } [(set_attr "length" "8")]) + +;; +;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u] +;; +(define_insn "mve_vldrbq_gather_offset_z_" + [(set (match_operand:MVE_2 0 "s_register_operand" "=3D&w") + (unspec:MVE_2 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRBGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[4]; + ops[0] =3D operands[0]; + ops[1] =3D operands[1]; + ops[2] =3D operands[2]; + ops[3] =3D operands[3]; + if (!strcmp ("","s") && =3D=3D 8) + output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops); + else + output_asm_insn ("vpst\n\tvldrbt.\t%q0, [%m1, %q2]",= ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrbq_z_s vldrbq_z_u] +;; +(define_insn "mve_vldrbq_z_" + [(set (match_operand:MVE_2 0 "s_register_operand" "=3Dw") + (unspec:MVE_2 [(match_operand: 1 "memory_operand" "Us") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VLDRBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D operands[1]; + output_asm_insn ("vpst\n\tvldrbt.\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u] +;; +(define_insn "mve_vldrwq_gather_base_z_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=3D&w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:HI 3 "vpr_register_operand" "Up")] + VLDRWGBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] =3D operands[0]; + ops[1] =3D operands[1]; + ops[2] =3D operands[2]; + output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); + return ""; +} + [(set_attr "length" "8")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_z_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..ce1b2b241989449e0bfee0f5a37= 8eb9b5a3e250a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s1= 6.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_s16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.s16" } } */ + +int16x8_t +foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_z_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..b79e1c8961cb52b4e16351064ee= 8f2e1be1baae5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s3= 2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_s32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.s32" } } */ + +int32x4_t +foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse= t_z_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..816634a7086ce290048a669144e= 715de03eed71c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8= .c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_s8 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ + +int8x16_t +foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_z_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..67722400bb04be883b89d3a8820= 23ef18b1e1c7d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u1= 6.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_u16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u16" } } */ + +uint16x8_t +foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_z_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..ed174404330e13e017edd07883d= bdb261300f23b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u3= 2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_u32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u32" } } */ + +uint32x4_t +foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse= t_z_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..1ac9f4ee3669222020b6de6b8e8= 9463128b61acd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8= .c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z_u8 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ + +uint8x16_t +foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) +{ + return vldrbq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..4fd604ed27da1d686f60b76c6a6= 6a5377b32ed3c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_s16 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..faae9e17c15cc60d72a582e4f34= 1dd2e132c4f7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_s32 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..1bb0bed237f936739395d48be95= 09393a888ae3d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_s8 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..50e18a3cecc98fe83727b9256e1= 4e8dd1088aa61 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_u16 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..78590dda496acb26d8eeff27393= 2541f7f1a3869 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_u32 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..54192ae94af60bbb2525d0f3dc8= 30d603de69fb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base, mve_pred16_t p) +{ + return vldrbq_z_u8 (base, p); +} + +/* { dg-final { scan-assembler "vldrbt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base= _z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z= _s32.c new file mode 100644 index 0000000000000000000000000000000000000000..3bb1ba826f309e53810aa675e54= 42d2aeb15f4b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (uint32x4_t addr, mve_pred16_t p) +{ + return vldrwq_gather_base_z_s32 (addr, 4, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base= _z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z= _u32.c new file mode 100644 index 0000000000000000000000000000000000000000..2a92e4d915fb77c42efd9be0ab0= 4f43dc836a4d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t addr, mve_pred16_t p) +{ + return vldrwq_gather_base_z_u32 (addr, 4, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ --_002_DBBPR08MB477535B6B4E27D3FF77437CF9B710DBBPR08MB4775eurp_ Content-Type: text/plain; name="diff23.patch" Content-Description: diff23.patch Content-Disposition: attachment; filename="diff23.patch"; size=24735; creation-date="Thu, 14 Nov 2019 19:13:21 GMT"; modification-date="Thu, 14 Nov 2019 19:13:21 GMT" Content-ID: <0B65E1304D808B4DB36CF5A904648F0E@eurprd08.prod.outlook.com> Content-Transfer-Encoding: base64 Content-length: 33530 ZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYXJtL2FybS1idWlsdGlucy5jIGIv Z2NjL2NvbmZpZy9hcm0vYXJtLWJ1aWx0aW5zLmMKaW5kZXggYjU2MzkwNTFi ZjA3Nzg1ZDkwNmVkNTk2ZTA4ZDY3MGY0ZGUxYTY3ZS4uYzNkMTIzNzVkMmZi YzkzM2FkMzNmN2ExNWEzYmJmNTMwNzlkMDYzOSAxMDA2NDQKLS0tIGEvZ2Nj L2NvbmZpZy9hcm0vYXJtLWJ1aWx0aW5zLmMKKysrIGIvZ2NjL2NvbmZpZy9h cm0vYXJtLWJ1aWx0aW5zLmMKQEAgLTY1Myw2ICs2NTMsNDAgQEAgYXJtX2xk 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