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Thu, 14 Nov 2019 19:13:05 +0000 From: Srinath Parvathaneni To: "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov Subject: [PATCH][ARM][GCC][2/2x]: MVE intrinsics with binary operands. Date: Thu, 14 Nov 2019 19:13:00 -0000 Message-ID: References: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> In-Reply-To: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-PUrlCount: 1 x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:1247;OLM:1247; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(1496009)(4636009)(39860400002)(396003)(366004)(376002)(346002)(136003)(54534003)(199004)(189003)(81156014)(316002)(81166006)(30864003)(2501003)(44832011)(4326008)(74316002)(7696005)(99286004)(478600001)(186003)(11346002)(26005)(54906003)(76176011)(52536014)(5660300002)(446003)(25786009)(71190400001)(71200400001)(33656002)(66946007)(52116002)(305945005)(66556008)(7736002)(66446008)(66476007)(66616009)(64756008)(256004)(5024004)(9686003)(966005)(5640700003)(3846002)(66066001)(4001150100001)(6916009)(86362001)(486006)(6506007)(6436002)(14454004)(8936002)(2906002)(6116002)(2351001)(55016002)(8676002)(102836004)(386003)(476003)(6306002)(2004002)(579004)(559001)(569006);DIR:OUT;SFP:1101;SCL:1;SRVR:DBBPR08MB4807;H:DBBPR08MB4775.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: aJf/xl16AejHI6cRyF5kHxzsZD59z3czsVAwwq19VzXklVXVfo5zB6p9Pe0vpkl0Ootyh+wTYZXYOjvJvPsgxxdVtVQuxS+DG95I1MeHhkh7nygM4ae3gXzPqCWPnZ/mwrQx+p5unVVqtnj0imS8/O0Yy8zXpJ1u/u79GiVS/kZO/2oV4tU0w11bogPQUo+S33UcQt5iQqke5L+C7slukT2u8dS62Q/kMZwR6CCm8f/EJBQn4faJrqynK4KSEmo53qWkJVaD9zV1wimbgPE1+XtJkD8fkjqv/9kAkUGyuwvua7lZ9vQoJNADUxlSuaBFGQwrk6+4NVsjqE+Ns5BmAA33F6l2sL3lJApx+uoymHRkHV0WBEwdey8RTZj307UtjBqRlJ38A8pYH2uBFreu7YYAFqFnxkII94+X0qbxaBp61ZZt89K/gvqNoVa9wg1UNYwZlnM9VT5x73Zxvtx8PBa8aUHHH7Z/5uV0teRk6MU= Content-Type: multipart/mixed; boundary="_002_DBBPR08MB477547A0F24CD6A21C6977649B710DBBPR08MB4775eurp_" MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; Return-Path: Srinath.Parvathaneni@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT064.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 3c618b86-fda3-4912-b461-08d76936ad2b X-IsSubscribed: yes X-SW-Source: 2019-11/txt/msg01254.txt.bz2 --_002_DBBPR08MB477547A0F24CD6A21C6977649B710DBBPR08MB4775eurp_ Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable Content-length: 33195 Hello, This patch supports following MVE ACLE intrinsics with binary operands. vcvtq_n_s16_f16, vcvtq_n_s32_f32, vcvtq_n_u16_f16, vcvtq_n_u32_f32, vcreate= q_u8, vcreateq_u16, vcreateq_u32, vcreateq_u64, vcreateq_s8, vcreateq_s16, vcreat= eq_s32, vcreateq_s64, vshrq_n_s8, vshrq_n_s16, vshrq_n_s32, vshrq_n_u8, vshrq_n_u16= , vshrq_n_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more d= etails. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/heli= um/mve-intrinsics In this patch new constraints "Rb" and "Rf" are added, which checks the con= stant is with in the range of 1 to 8 and 1 to 32 respectively. Also a new predicates "mve_imm_8" and "mve_imm_32" are added, to check the = the matching constraint Rb and Rf respectively. Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-10-21 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define qualifier for binary operands. (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro. (vcvtq_n_s32_f32): Likewise. (vcvtq_n_u16_f16): Likewise. (vcvtq_n_u32_f32): Likewise. (vcreateq_u8): Likewise. (vcreateq_u16): Likewise. (vcreateq_u32): Likewise. (vcreateq_u64): Likewise. (vcreateq_s8): Likewise. (vcreateq_s16): Likewise. (vcreateq_s32): Likewise. (vcreateq_s64): Likewise. (vshrq_n_s8): Likewise. (vshrq_n_s16): Likewise. (vshrq_n_s32): Likewise. (vshrq_n_u8): Likewise. (vshrq_n_u16): Likewise. (vshrq_n_u32): Likewise. (__arm_vcreateq_u8): Define intrinsic. (__arm_vcreateq_u16): Likewise. (__arm_vcreateq_u32): Likewise. (__arm_vcreateq_u64): Likewise. (__arm_vcreateq_s8): Likewise. (__arm_vcreateq_s16): Likewise. (__arm_vcreateq_s32): Likewise. (__arm_vcreateq_s64): Likewise. (__arm_vshrq_n_s8): Likewise. (__arm_vshrq_n_s16): Likewise. (__arm_vshrq_n_s32): Likewise. (__arm_vshrq_n_u8): Likewise. (__arm_vshrq_n_u16): Likewise. (__arm_vshrq_n_u32): Likewise. (__arm_vcvtq_n_s16_f16): Likewise. (__arm_vcvtq_n_s32_f32): Likewise. (__arm_vcvtq_n_u16_f16): Likewise. (__arm_vcvtq_n_u32_f32): Likewise. (vshrq_n): Define polymorphic variant. * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Use it. (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. * config/arm/constraints.md (Rb): Define constraint to check constant is in the range of 1 to 8. (Rf): Define constraint to check constant is in the range of 1 to 32. * config/arm/mve.md (mve_vcreateq_): Define RTL pattern. (mve_vshrq_n_): Likewise. (mve_vcvtq_n_from_f_): Likewise. * config/arm/predicates.md (mve_imm_8): Define predicate to check the matching constraint Rb. (mve_imm_32): Define predicate to check the matching constraint Rf. gcc/testsuite/ChangeLog: 2019-10-21 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise. ############### Attachment also inlined for ease of reply ##########= ##### diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index c2dad057d1365914477c64d559aa1fd1c32bbf19..ec56dbcdd66662bb1de69614218= 6955d75570772 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -373,6 +373,24 @@ arm_binop_none_unone_unone_qualifiers[SIMD_MAX_BUILTIN= _ARGS] #define BINOP_NONE_UNONE_UNONE_QUALIFIERS \ (arm_binop_none_unone_unone_qualifiers) =20 +static enum arm_type_qualifiers +arm_binop_unone_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_unsigned, qualifier_unsigned, qualifier_immediate }; +#define BINOP_UNONE_UNONE_IMM_QUALIFIERS \ + (arm_binop_unone_unone_imm_qualifiers) + +static enum arm_type_qualifiers +arm_binop_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned }; +#define BINOP_UNONE_UNONE_UNONE_QUALIFIERS \ + (arm_binop_unone_unone_unone_qualifiers) + +static enum arm_type_qualifiers +arm_binop_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_unsigned, qualifier_none, qualifier_immediate }; +#define BINOP_UNONE_NONE_IMM_QUALIFIERS \ + (arm_binop_unone_none_imm_qualifiers) + /* End of Qualifier for MVE builtins. */ =20 /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 15b7ada025fe57b682f3873f0f275c43a30d1273..0318a2cd8c3cdea430a32506e75= a5aceb4d3a475 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -207,6 +207,24 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vcvtq_n_f32_u32(__a, __imm6) __arm_vcvtq_n_f32_u32(__a, __imm6) #define vcreateq_f16(__a, __b) __arm_vcreateq_f16(__a, __b) #define vcreateq_f32(__a, __b) __arm_vcreateq_f32(__a, __b) +#define vcvtq_n_s16_f16(__a, __imm6) __arm_vcvtq_n_s16_f16(__a, __imm6) +#define vcvtq_n_s32_f32(__a, __imm6) __arm_vcvtq_n_s32_f32(__a, __imm6) +#define vcvtq_n_u16_f16(__a, __imm6) __arm_vcvtq_n_u16_f16(__a, __imm6) +#define vcvtq_n_u32_f32(__a, __imm6) __arm_vcvtq_n_u32_f32(__a, __imm6) +#define vcreateq_u8(__a, __b) __arm_vcreateq_u8(__a, __b) +#define vcreateq_u16(__a, __b) __arm_vcreateq_u16(__a, __b) +#define vcreateq_u32(__a, __b) __arm_vcreateq_u32(__a, __b) +#define vcreateq_u64(__a, __b) __arm_vcreateq_u64(__a, __b) +#define vcreateq_s8(__a, __b) __arm_vcreateq_s8(__a, __b) +#define vcreateq_s16(__a, __b) __arm_vcreateq_s16(__a, __b) +#define vcreateq_s32(__a, __b) __arm_vcreateq_s32(__a, __b) +#define vcreateq_s64(__a, __b) __arm_vcreateq_s64(__a, __b) +#define vshrq_n_s8(__a, __imm) __arm_vshrq_n_s8(__a, __imm) +#define vshrq_n_s16(__a, __imm) __arm_vshrq_n_s16(__a, __imm) +#define vshrq_n_s32(__a, __imm) __arm_vshrq_n_s32(__a, __imm) +#define vshrq_n_u8(__a, __imm) __arm_vshrq_n_u8(__a, __imm) +#define vshrq_n_u16(__a, __imm) __arm_vshrq_n_u16(__a, __imm) +#define vshrq_n_u32(__a, __imm) __arm_vshrq_n_u32(__a, __imm) #endif =20 __extension__ extern __inline void @@ -753,6 +771,104 @@ __arm_vpnot (mve_pred16_t __a) return __builtin_mve_vpnothi (__a); } =20 +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_u8 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_uv16qi (__a, __b); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_u16 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_uv8hi (__a, __b); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_u32 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_uv4si (__a, __b); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_u64 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_uv2di (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_s8 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_sv16qi (__a, __b); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_s16 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_sv8hi (__a, __b); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_s32 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_sv4si (__a, __b); +} + +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcreateq_s64 (uint64_t __a, uint64_t __b) +{ + return __builtin_mve_vcreateq_sv2di (__a, __b); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_s8 (int8x16_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_sv16qi (__a, __imm); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_s16 (int16x8_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_sv8hi (__a, __imm); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_s32 (int32x4_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_sv4si (__a, __imm); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_u8 (uint8x16_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_uv16qi (__a, __imm); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_u16 (uint16x8_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_uv8hi (__a, __imm); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshrq_n_u32 (uint32x4_t __a, const int __imm) +{ + return __builtin_mve_vshrq_n_uv4si (__a, __imm); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ =20 __extension__ extern __inline void @@ -1165,6 +1281,34 @@ __arm_vcreateq_f32 (uint64_t __a, uint64_t __b) return __builtin_mve_vcreateq_fv4sf (__a, __b); } =20 +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6) +{ + return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6); +} + #endif =20 enum { @@ -1598,6 +1742,16 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__= p0, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__= p0, int32x4_t)));}) =20 +#define vshrq(p0,p1) __arm_vshrq(p0,p1) +#define __arm_vshrq(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshrq_n_s8 (__ARM_mve_coerce(__= p0, int8x16_t), p1), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshrq_n_s16 (__ARM_mve_coerce(_= _p0, int16x8_t), p1), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshrq_n_s32 (__ARM_mve_coerce(_= _p0, int32x4_t), p1), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshrq_n_u8 (__ARM_mve_coerce(_= _p0, uint8x16_t), p1), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_n_u16 (__ARM_mve_coerce(= __p0, uint16x8_t), p1), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_n_u32 (__ARM_mve_coerce(= __p0, uint32x4_t), p1));}) + #endif /* MVE Floating point. */ =20 #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_b= uiltins.def index 8d1e4fac3d75e87fbe334e64e1073cb1fef0d96d..eae37ba831361401241ed919501= 69f06dee29c3e 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -6,7 +6,7 @@ =20 GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your + by the Free Software Foundation; either version 3, or (at your option) any later version. =20 GCC is distributed in the hope that it will be useful, but WITHOUT @@ -81,3 +81,9 @@ VAR2 (BINOP_NONE_NONE_NONE, vbrsrq_n_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_to_f_s, v8hf, v4sf) VAR2 (BINOP_NONE_UNONE_IMM, vcvtq_n_to_f_u, v8hf, v4sf) VAR2 (BINOP_NONE_UNONE_UNONE, vcreateq_f, v8hf, v4sf) +VAR2 (BINOP_UNONE_NONE_IMM, vcvtq_n_from_f_u, v8hi, v4si) +VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_from_f_s, v8hi, v4si) +VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di) +VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di) +VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 86cd82334533acbe58be4a0c547cf38737d2bb84..978674991d4bf0fa2082f38a630= f2c9e845a7881 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -35,7 +35,7 @@ ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, D= i, ;; Dt, Dp, Dz, Tu ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe -;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd +;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb ;; in all states: Pf, Pg, UM, U1 =20 ;; The following memory constraints have been used: @@ -56,6 +56,16 @@ (and (match_code "const_int") (match_test "TARGET_HAVE_MVE && ival >=3D 1 && ival <=3D 16"))) =20 +(define_constraint "Rb" + "@internal In Thumb-2 state a constant in range 1 to 8" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && ival >=3D 1 && ival <=3D 8"))) + +(define_constraint "Rf" + "@internal In Thumb-2 state a constant in range 1 to 32" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && ival >=3D 1 && ival <=3D 32"))) + (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") =20 diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 06701b024dabae85446bb60060a8b331e540cd6d..4ae7646cf20683ec147af11f398= d7460bd65f7ba 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -22,6 +22,7 @@ (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) (define_mode_iterator MVE_0 [V8HF V4SF]) +(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI]) (define_mode_iterator MVE_3 [V16QI V8HI]) (define_mode_iterator MVE_2 [V16QI V8HI V4SI]) (define_mode_iterator MVE_5 [V8HI V4SI]) @@ -38,7 +39,8 @@ VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F - VSUBQ_N_F]) + VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U + VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U]) =20 (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -55,10 +57,16 @@ (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u") (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u") (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s") - (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")]) + (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u") + (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s") + (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") + (VCVTQ_N_FROM_F_U "u")]) =20 (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64")]) +(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16") + (V4SI "mve_imm_32")]) +(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")]) =20 (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -79,6 +87,9 @@ (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) (define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q]) (define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U]) +(define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S]) +(define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U]) +(define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U]) =20 (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "s_register_operand" "=3Dw,w,r,w,w,r,w") @@ -743,3 +754,48 @@ "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" [(set_attr "type" "mve_move") (set_attr "length""8")]) + +;; +;; [vcreateq_u, vcreateq_s]) +;; +(define_insn "mve_vcreateq_" + [ + (set (match_operand:MVE_1 0 "s_register_operand" "=3Dw") + (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r") + (match_operand:DI 2 "s_register_operand" "r")] + VCREATEQ)) + ] + "TARGET_HAVE_MVE" + "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +;; +;; [vshrq_n_s, vshrq_n_u]) +;; +(define_insn "mve_vshrq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=3Dw") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:SI 2 "" "")] + VSHRQ_N)) + ] + "TARGET_HAVE_MVE" + "vshr.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]) +;; +(define_insn "mve_vcvtq_n_from_f_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=3Dw") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w") + (match_operand:SI 2 "mve_imm_16" "Rd")] + VCVTQ_N_FROM_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvt.%#.f%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 80a44bb32cbce1ee3f850a44b70a0e4ceed548be..2e038705b3594ef8756bbb56c46= d3285261e946e 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -35,6 +35,14 @@ (define_predicate "mve_imm_16" (match_test "satisfies_constraint_Rd (op)")) =20 +;; True for immediates in the range of 1 to 8 for MVE. +(define_predicate "mve_imm_8" + (match_test "satisfies_constraint_Rb (op)")) + +;; True for immediates in the range of 1 to 32 for MVE. +(define_predicate "mve_imm_32" + (match_test "satisfies_constraint_Rf (op)")) + ; Predicate for stack protector guard's address in ; stack_protect_combined_set_insn and stack_protect_combined_test_insn pat= terns (define_predicate "guard_addr_operand" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..fad5de2e5d2603abac244a6554e= e2351c3b05ddb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_s16 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..b6013be8481b8d8a800eca2a2e2= 75720283586d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_s32 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c new file mode 100644 index 0000000000000000000000000000000000000000..74372bef4eaa53772765029ce20= e51ef3ecb80d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int64x2_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_s64 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..9884f0435780c7895c0cf1825d4= d024f496e5a33 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_s8 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..cc60f6cd4dd7370dae5245a6499= 383659705af7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_u16 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..43a49bc0a4a86c7a090151e7a5f= 4b6887496b520 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_u32 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c new file mode 100644 index 0000000000000000000000000000000000000000..d798273dab689fc95746c0788d3= 1c7d56244dd67 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint64x2_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_u64 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..7bb6a75ab8a2d52834798f39e8f= ff1e43ec0cfd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint64_t a, uint64_t b) +{ + return vcreateq_u8 (a, b); +} + +/* { dg-final { scan-assembler "vmov" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c = b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..f40561848707ba059506fb532b0= 52489823262cb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtq_n_s16_f16 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c = b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..1bb98c254f5ba72af2416b952c5= c96b315d148a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtq_n_s32_f32 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c = b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..7bded9d70b55b06a872789118df= 65f2cced0d7a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtq_n_u16_f16 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c = b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..cbcf93b3e102d2e47c18792d641= f0e8f56fbdbe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a) +{ + return vcvtq_n_u32_f32 (a, 1); +} + +/* { dg-final { scan-assembler "vcvt.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..71950e35e9f1a9185f45858bb9f= 4e5def844644d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vshrq_n_s16 (a, 16); +} + +/* { dg-final { scan-assembler "vshr.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vshrq (a, 16); +} + +/* { dg-final { scan-assembler "vshr.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..b31d7a479e778f8ef9bc50c75b0= 7983de7f93fe2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vshrq_n_s32 (a, 32); +} + +/* { dg-final { scan-assembler "vshr.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vshrq (a, 32); +} + +/* { dg-final { scan-assembler "vshr.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..461a268501f86ad9ead5dbe68b2= 1c438d6257dbe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vshrq_n_s8 (a, 8); +} + +/* { dg-final { scan-assembler "vshr.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vshrq (a, 8); +} + +/* { dg-final { scan-assembler "vshr.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..97c6323b4c645fb78fb28e4ab8e= f83855fb60037 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vshrq_n_u16 (a, 16); +} + +/* { dg-final { scan-assembler "vshr.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vshrq (a, 16); +} + +/* { dg-final { scan-assembler "vshr.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..42006566f635b81268e01d3e184= 26bc294484c5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vshrq_n_u32 (a, 32); +} + +/* { dg-final { scan-assembler "vshr.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t a) +{ + return vshrq (a, 32); +} + +/* { dg-final { scan-assembler "vshr.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..25679297b6d5165fabfd77953f4= 8b0af36867dad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vshrq_n_u8 (a, 8); +} + +/* { dg-final { scan-assembler "vshr.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vshrq (a, 8); +} + +/* { dg-final { scan-assembler "vshr.u8" } } */ --_002_DBBPR08MB477547A0F24CD6A21C6977649B710DBBPR08MB4775eurp_ Content-Type: text/plain; name="diff09.patch" Content-Description: diff09.patch Content-Disposition: attachment; filename="diff09.patch"; size=28361; creation-date="Thu, 14 Nov 2019 19:13:05 GMT"; modification-date="Thu, 14 Nov 2019 19:13:05 GMT" Content-ID: <4A4CED1DCC94E84A8E440124CB54E18D@eurprd08.prod.outlook.com> Content-Transfer-Encoding: base64 Content-length: 38447 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